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? 2013-2015 microchip technology inc. ds70005127c-page 1 dspic33epxxgs50x family operating conditions 3.0v to 3.6v, -40c to +85c, dc to 70 mips 3.0v to 3.6v, -40c to +125c, dc to 60 mips flash architecture dual partition flash program memory with live update (64-kbyte devices): - supports programming while operating - supports partition soft swap core: 16-bit dspic33e cpu code-efficient (c and assembly) architecture two 40-bit wide accumulators single-cycle (mac/mpy) with dual data fetch single-cycle mixed-sign mul plus hardware divide 32-bit multiply support two additional working register sets (reduces context switching) clock management 0.9% internal oscillator programmable plls and oscillator clock sources fail-safe clock monitor (fscm) independent watchdog timer (wdt) fast wake-up and start-up power management low-power management modes (sleep, idle, doze) integrated power-on reset and brown-out reset 0.5 ma/mhz dynamic current (typical) 10 a i pd current (typical) high-speed pwm five pwm generators (two outputs per generator) individual time base and duty cycle for each pwm 1.04 ns pwm resolution (frequency, duty cycle, dead time and phase) supports center-aligned, redundant, complementary and true independent output modes independent fault and current-limit inputs output override control pwm support for ac/dc, dc/dc, inverters, pfc and lighting advanced analog features high-speed adc module: - 12-bit with 4 dedicated sar adc cores and one shared sar adc core - configurable resolution (up to 12-bit) for each adc core - up to 3.25 msps conversion rate per channel at 12-bit resolution - 12 to 22 single-ended inputs - dedicated result buffer for each analog channel - flexible and independent adc trigger sources - two digital comparators - two oversampling filters for increased resolution four rail-to-rail comparators with hysteresis: - dedicated 12-bit digital-to-analog converter (dac) for each analog comparator - up to two dac reference outputs - up to two external reference inputs two programmable gain amplifiers: - single-ended or independent ground reference - five selectable gains (4x, 8x, 16x, 32x and 64x) - 40 mhz gain bandwidth interconnected smps peripherals reduces cpu interaction to improve performance flexible pwm trigger options for adc conversions high-speed comparator truncates pwm (15 ns typical): - supports cycle-by-cycle current mode control - current reset mode (variable frequency) timers/output compare/input capture five 16-bit and up to two 32-bit timers/counters four output compare (oc) modules, configurable as timers/counters four input capture (ic) modules 16-bit digital signal controllers for digital power applications with interconnected high-speed pwm, adc, pga and comparators downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 2 ? 2013-2015 microchip technology inc. communication interfaces two uart modules (15 mbps): - supports lin/j2602 protocols and irda ? two 4-wire spi modules (15 mbps) two i 2 c modules (up to 1 mbaud) with smbus support input/output constant-current source (10 a nominal) sink/source up to 12ma/15ma, respectively; pin-specific for standard v oh /v ol 5v tolerant pins selectable, open-drain pull-ups and pull-downs external interrupts on all i/o pins peripheral pin select (pps) to allow function remap with six virtual i/os qualification and class b support aec-q100 revg (grade 1, -40c to +125c) class b safety library, iec 60730 the 6x6x0.5 mm uqfn package is designed and optimized to ease ipc9592b 2nd level temperature cycle qualification debugger development support in-circuit and in-application programming five program and three complex data breakpoints ieee 1149.2 compatible (jtag) boundary scan trace and run-time watch device pins program memory bytes ram (bytes) general purpose i/o (gpio) remappable peripherals i 2 c 12-bit adc pga analog comparator dac output constant-current source packages timers ( 1 ) input capture output compare uart spi pwm ( 2 ) external interrupts ( 3 ) reference clock analog inputs s&h circuits dspic33ep16gs502 28 16k 2k 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 soic, qfn-s, uqfn dspic33ep32gs502 28 32k 4k 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 dspic33ep64gs502 28 64k 8k 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 dspic33ep16gs504 44 16k 2k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 qfn, tqfp dspic33ep32gs504 44 32k 4k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dspic33ep64gs504 44 64k 8k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dspic33ep16gs505 48 16k 2k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 tqfp dspic33ep32gs505 48 32k 4k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dspic33ep64gs505 48 64k 8k 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dspic33ep16gs506 64 16k 2k 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 tqfp dspic33ep32gs506 64 32k 4k 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 dspic33ep64gs506 64 64k 8k 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 note 1: the external clock for timer1, timer2 and timer3 is remappable. 2: pwm4 and pwm5 are remappable on all devices except the 64-pin devices. 3: external interrupts, int0 and int4, are not remappable. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 3 dspic33epxxgs50x family pin diagrams 28-pin soic mclr av dd ra0 av ss ra1 ra3 ra2 ra4 rb0 rb14 rb9 rb13 rb10 rb12 rb11 rb1 v cap rb2 v ss rb3 rb7 rb4 rb6 v dd rb5 rb8 rb15 v ss dspic33epxxgs502 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see table 10-1 and ta b l e 1 0 - 2 for the complete list of remappable sources. pin pin function pin pin function 1mclr 15 pgec3/scl2/ rp47 /rb15 2 an0/pga1p1/cmp1a/ra0 16 tdo/an19/pga2n2/ rp37 /rb5 3 an1/pga1p2/pga2p1/cmp1b/ra1 17 pged1/tdi/an20/scl1/ rp38 /rb6 4 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 18 pgec1/an21/sda1/ rp39 /rb7 5 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 19 v ss 6 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 20 v cap 7 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 21 tms/pwm3h/ rp43 /rb11 8vss 22tck/pwm3l/ rp44 / r b12 9 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 23 pwm2h/ rp45 /rb13 10 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 24 pwm2l/ rp46 /rb14 11 pged2/an18/dacout1/int0/ rp35 /rb3 25 pwm1h/ra4 12 pgec2/adtrg31/extref1/rp36/rb4 26 pwm1l/ra3 13 v dd 27 av ss 14 pged3/sda2/rp40/rb8 28 av dd downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 4 ? 2013-2015 microchip technology inc. pin diagrams (continued) legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see table 10-1 and ta b l e 1 0 - 2 for the complete list of remappable sources. pin pin function pin pin function 1 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 15 pgec1/an21/sda1/ rp39 /rb7 2 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 16 v ss 3 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 17 v cap 4 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 18 tms/pwm3h/ rp43 /rb11 5 vss 19 tck/pwm3l/ rp44 / r b12 6 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 20 pwm2h/ rp45 /rb13 7 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 21 pwm2l/ rp46 /rb14 8 pged2/an18/dacout1/int0/ rp35 /rb3 22 pwm1h/ra4 9 pgec2/adtrg31/extref1/rp36/rb4 23 pwm1l/ra3 10 v dd 24 av ss 11 pged3/sda2/rp40/rb8 25 av dd 12 pgec3/scl2/ rp47 /rb15 26 mclr 13 tdo/an19/pga2n2/ rp37 /rb5 27 an0/pga1p1/cmp1a/ra0 14 pged1/tdi/an20/scl1/ rp38 /rb6 28 an1/pga1p2/pga2p1/cmp1b/ra1 28-pin qfn-s, uqfn 21 20 19 18 17 16 15 1 2 3 4 5 6 7 24 11 10 9 8 25 26 28 22 23 13 12 27 14 dspic33epxxgs502 rb6 rb5 rb15 rb8 v dd rb4 rb3 rb14 rb13 rb12 rb11 v cap v ss rb7 ra4 ra3 av ss av dd mclr ra0 ra1 ra2rb0 v ss rb1rb2 rb9 rb10 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 5 dspic33epxxgs50x family pin diagrams (continued) dspic33epxxgs504 44-pin qfn 44 12 11 23 24 25 26 27 28 29 30 31 32 33 13 14 15 16 17 18 19 20 21 22 10 9 8 7 6 5 4 3 2 1 43 42 41 40 39 38 37 36 35 34 ra2 rb0 rb9 rb10 rc9 rc10 v dd v ss rc1 rb1 rb2 rb6rb5 rb15 rb8 v dd v ss rc8rc7 rc2 rb4 rb3 rb14 rb13 rb12 rb11 v cap v ss rc3 rc6 rc5 rc4 rb7 ra4ra3 rc0 rc13 av ss av dd mclr rc11 rc12 ra0ra1 legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see ta b l e 1 0 - 1 and table 10-2 for the complete list of remappable sources. pin pin function pin pin function 1 pgec1/an21/sda1/ rp39 /rb7 23 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 2an1alt/ rp52 /rc4 24 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 3an0alt/ rp53 /rc5 25 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 4an17/ rp54 /rc6 26 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 5 rp51 /rc3 27 an11/pga1n3/ rp57 /rc9 6v ss 28 an10/pga1p4/extref2/ rp58 /rc10 7v cap 29 v dd 8tms/pwm3h/ rp43 /rb11 30 v ss 9tck/pwm3l/ rp44 /rb12 31 an8/pga2p4/cmp4c/ rp49 /rc1 10 pwm2h/ rp45 /rb13 32 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 11 pwm2l/ rp46 /rb14 33 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 12 pwm1h/ra4 34 pged2/an18/dacout1/int0/ rp35 /rb3 13 pwm1l/ra3 35 pgec2/adtrg31/ rp36 /rb4 14 flt12/ rp48 /rc0 36 an9/cmp4d/extref1/ rp50 /rc2 15 flt11/ rp61 /rc13 37 asda1/ rp55 /rc7 16 av ss 38 ascl1/ rp56 /rc8 17 av dd 39 v ss 18 mclr 40 v dd 19 an12/isrc1/ rp59 /rc11 41 pged3/sda2/ rp40 /rb8 20 an14/pga2n3/ rp60 /rc12 42 pgec3/scl2/ rp47 /rb15 21 an0/pga1p1/cmp1a/ra0 43 tdo/an19/pga2n2/ rp37 /rb5 22 an1/pga1p2/pga2p1/cmp1b/ra1 44 pged1/tdi/an20/scl1/ rp38 /rb6 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 6 ? 2013-2015 microchip technology inc. pin diagrams (continued) 44-pin tqfp ra2 rb0 rb9 rb10 rc9 rc10 v dd v ss rc1 rb1 rb2 rb6rb5 rb15 rb8 v dd v ss rc8rc7 rc2 rb4 rb3 rb14 rb13 rb12 rb11 v cap v ss rc3 rc6 rc5 rc4 rb7 ra4ra3 rc0 rc13 av ss av dd mclr rc11 rc12 ra0ra1 legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see ta b l e 1 0 - 1 and table 10-2 for the complete list of remappable sources. pin pin function pin pin function 1 pgec1/an21/sda1/ rp39 /rb7 23 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 2an1alt/ rp52 /rc4 24 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 3an0alt/ rp53 /rc5 25 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 4an17/ rp54 /rc6 26 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 5 rp51 /rc3 27 an11/pga1n3/ rp57 /rc9 6v ss 28 an10/pga1p4/extref2/ rp58 /rc10 7v cap 29 v dd 8tms/pwm3h/ rp43 /rb11 30 v ss 9tck/pwm3l/ rp44 /rb12 31 an8/pga2p4/cmp4c/ rp49 /rc1 10 pwm2h/ rp45 /rb13 32 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 11 pwm2l/ rp46 /rb14 33 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 12 pwm1h/ra4 34 pged2/an18/dacout1/int0/ rp35 /rb3 13 pwm1l/ra3 35 pgec2/adtrg31/ rp36 /rb4 14 flt12/ rp48 /rc0 36 an9/cmp4d/extref1/ rp50 /rc2 15 flt11/ rp61 /rc13 37 asda1/ rp55 /rc7 16 av ss 38 ascl1/ rp56 /rc8 17 av dd 39 v ss 18 mclr 40 v dd 19 an12/isrc1/ rp59 /rc11 41 pged3/sda2/ rp40 /rb8 20 an14/pga2n3/ rp60 /rc12 42 pgec3/scl2/ rp47 /rb15 21 an0/pga1p1/cmp1a/ra0 43 tdo/an19/pga2n2/ rp37 /rb5 22 an1/pga1p2/pga2p1/cmp1b/ra1 44 pged1/tdi/an20/scl1/ rp38 /rb6 4443 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 1213 14 15 16 17 18 19 20 21 22 dspic33epxxgs504 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 7 dspic33epxxgs50x family pin diagrams (continued) 48-pin tqfp legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see ta b l e 1 0 - 1 and table 10-2 for the complete list of remappable sources. pin pin function pin pin function 1 pgec1/an21/sda1/ rp39 /rb7 25 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 2an1alt/ rp52 /rc4 26 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 3an0alt/ rp53 /rc5 27 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 4an17/ rp54 /rc6 28 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 5 rp51 /rc3 29 an11/pga1n3/ rp57 /rc9 6v ss 30 an10/pga1p4/extref2/ rp58 /rc10 7v cap 31 v dd 8n/c 32v ss 9tms/pwm3h/ rp43 /rb11 33 n/c 10 tck/pwm3l/ rp44 /rb12 34 an8/pga2p4/cmp4c/ rp49 /rc1 11 pwm2h/ rp45 /rb13 35 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 12 pwm2l/ rp46 /rb14 36 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 13 pwm1h/ra4 37 pged2/an18/dacout1/int0/ rp35 /rb3 14 pwm1l/ra3 38 pgec2/adtrg31/ rp36 /rb4 15 flt12/ rp48 /rc0 39 an9/cmp4d/extref1/ rp50 /rc2 16 flt11/ rp61 /rc13 40 asda1/ rp55 /rc7 17 n/c 41 ascl1/ rp56 /rc8 18 av ss 42 v ss 19 av dd 43 v dd 20 mclr 44 n/c 21 an12/isrc1/ rp59 /rc11 45 pged3/sda2/ rp40 /rb8 22 an14/pga2n3/ rp60 /rc12 46 pgec3/scl2/ rp47 /rb15 23 an0/pga1p1/cmp1a/ra0 47 tdo/an19/pga2n2/ rp37 /rb5 24 an1/pga1p2/pga2p1/cmp1b/ra1 48 pged1/tdi/an20/scl1/ rp38 /rb6 1011 23 4 5 6 1 1920 21 22 23 1314 15 16 41 8 7 4746 45 44 43 42 1718 31 32 33 34 3525 26 27 28 29 30 3937 38 9 40 12 24 36 48 rb7 rc4rc5 rc6 rc3 v ss v cap n/c rb11 rb12 rb13 rb14 ra4ra3 rc0 rc13 av ss n/c av dd mclr rc11 rc12 ra0ra1 rb2 rb1 rc1 n/c vss v dd rc10 rc9 rb10 rb9 rb0 ra2 rb6rb5 rb15 rb8 n/c v dd v ss rc8rc7 rc2 rb4 rb3 dspic33epxxgs505 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 8 ? 2013-2015 microchip technology inc. pin diagrams (continued) 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin tqfp rc3 rd1rb14 rb13 v cap rb11 rd15 rb12rb7 rc4 v dd rd4rc5 rd6rd5 rc6 rb9 rb10 av dd av ss rd7 rd13 rc9 rc10 v ss v dd rc1 rb1rb3 rc15 rd2 rd3 ra4ra3 rc0 rc13rd10 mclr v ss v dd ra0ra1 ra2 rb0 rd12 rc11 rc12 rb6rd0 rb5 rd11 rb8 rd8 vss rd9 rd14 v dd rc8rc2 rc14 rb4 rc7 rb15 rb2 dspic33epxxgs506 legend: shaded pins are up to 5 vdc tolerant. rpn represents remappable peripheral functions. see table 10-1 and table 10-2 for the complete list of remappable sources. pin pin function pin pin function 1 pwm4l/rd3 33 pgec2/adtrg31/ rp36 /rb4 2 pwm1h/ra4 34 rp62 /rc14 3 pwm1l/ra3 35 an9/cmp4d/extref1/ rp50 /rc2 4 flt12/ rp48 /rc0 36 asda1/ rp55 /rc7 5 flt11/ rp61 /rc13 37 ascl1/ rp56 /rc8 6 flt10/rd10 38 v dd 7mclr 39 rd14 8 flt9/t5ck/rd12 40 rd9 9v ss 41 v ss 10 v dd 42 rd8 11 an12/isrc1/ rp59 /rc11 43 pged3/sda2/ rp40 /rb8 12 an14/pga2n3/ rp60 /rc12 44 pgec3/scl2/ rp47 /rb15 13 an0/pga1p1/cmp1a/ra0 45 int4/rd11 14 an1/pga1p2/pga2p1/cmp1b/ra1 46 tdo/an19/pga2n2/ rp37 /rb5 15 an2/pga1p3/pga2p2/cmp1c/cmp2a/ra2 47 t4ck/rd0 16 an3/pga2p3/cmp1d/cmp2b/ rp32 /rb0 48 pged1/tdi/an20/scl1/ rp38 /rb6 17 an4/cmp2c/cmp3a/isrc4/ rp41 /rb9 49 pgec1/an21/sda1/ rp39 /rb7 18 an5/cmp2d/cmp3b/isrc3/ rp42 /rb10 50 an1alt/ rp52 /rc4 19 av dd 51 an0alt/ rp53 /rc5 20 av ss 52 an17/ rp54 /rc6 21 an15/rd7 53 rd5 22 an13/dacout2/rd13 54 pwm5h/rd6 23 an11/pga1n3/ rp57 /rc9 55 pwm5l/ rp51 /rc3 24 an10/pga1p4/extref2/ rp58 /rc10 56 v cap 25 v ss 57 v dd 26 v dd 58 rd4 27 an8/pga2p4/cmp4c/ rp49 /rc1 59 rd15 28 osc1/clki/an6/cmp3c/cmp4a/isrc2/ rp33 /rb1 60 tms/pwm3h/ rp43 /rb11 29 osc2/clko/an7/pga1n2/cmp3d/cmp4b/ rp34 /rb2 61 tck/pwm3l/ rp44 / r b12 30 an16/rd2 62 pwm2h/ rp45 /rb13 31 asda2/ rp63 /rc15 63 pwm2l/ rp46 /rb14 32 pged2/an18/dacout1/ascl2/int0/rp35/rb3 64 pwm4h/rd1 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 9 dspic33epxxgs50x family table of contents 1.0 device overview ............................................................................ ............................................................................................ 11 2.0 guidelines for getting started with 16-bit digital signal cont rollers....................................................... ................................... 15 3.0 cpu.............................................................................................. .............................................................................................. 21 4.0 memory organization .......................................... ................................................... ............ ........................................................ 31 5.0 flash program memory.............................................................. .......................................... ...................................................... 77 6.0 resets ......................................................................................... ............................ .................................................................. 85 7.0 interrupt controller ................................................ ........................................................ ............................................................. 89 8.0 oscillator configuration ..................................... ........................................................................................................... ............ 103 9.0 power-saving features............................................................ ........................................... ..................................................... 115 10.0 i/o ports ....................................................................................... ........................... ................................................................. 125 11.0 timer1 .......................................................................................... ............................................................................................ 163 12.0 timer2/3 and timer4/5 ...................................... ................................................... ............ ....................................................... 167 13.0 input capture............................................ ................................................... ............... .............................................................. 171 14.0 output compare........................................................................... .................................. .......................................................... 175 15.0 high-speed pwm........................................................................... .................................. ........................................................ 181 16.0 serial peripheral interface (spi)........................................ .................................................. ..................................................... 207 17.0 inter-integrated circuit (i 2 c) ....................................................................................................... .............................................. 215 18.0 universal asynchronous receiver transmitter (uart) ............................... .......................................... .................................. 223 19.0 high-speed, 12-bit analog-to-digital converter (adc)... .................................................................... ..................................... 229 20.0 high-speed analog comparator .................................................... ........................................... ............................................... 263 21.0 programmable gain amplifier (pga) ................................................... ....................................... ............................................. 271 22.0 constant-current source ........................................................... ......................................... ..................................................... 275 23.0 special features ................................................... ........................................................ ........................................................... 277 24.0 instruction set summary ........................................................ ............................................ ...................................................... 289 25.0 development support............................................ ................................................... ......... ....................................................... 299 26.0 electrical characteristics ...................................................... ........................................... ......................................................... 303 27.0 dc and ac device characteristics graphs.................................. .................................................. .......................................... 349 28.0 packaging information.............................................................. ........................................ ........................................................ 353 appendix a: revision history.......................................... ................................................... ...... .......................................................... 377 index ................................................. ................................................... ...................... ....................................................................... 379 the microchip web site........................................................................... .............................. ............................................................ 385 customer change notification service ....................................... ................................................... . ................................................... 385 customer support............................................... ................................................... ............. ............................................................... 385 product identification system ............................................. ..................................................... .......................................................... 387 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 10 ? 2013-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the rev isi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 11 dspic33epxxgs50x family 1.0 device overview this document contains device-specific information for the dspic33epxxgs50x digital signal controller (dsc) devices. dspic33epxxgs50x devices contain extensive digital signal processor (dsp) functionality with a high-performance, 16-bit mcu architecture. figure 1-1 shows a general block diagram of the core and peripheral modules. table 1-1 lists the functions of the various pins shown in the pinout diagrams. figure 1-1: dspic33epxxgs50x family block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a com- prehensive resource. to complement the information in this data sheet, refer to the related section of the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. porta power-up timer oscillator start-up osc1/clki mclr v dd , v ss uart1, timing generation i2c1, adc timers input captures output compares av dd , av ss uart2 spi2 spi1, watchdog timer por/bor i2c2 pwms remappable pins pga1, pga2 cpu refer to figure 3-1 for cpu diagram details. 16 16 portb portc portd ports peripheral modules timer constant current source analog comparators 1-4 5x2 1-5 1-4 1-4 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 12 ? 2013-2015 microchip technology inc. table 1-1: pinout i/o descriptions pin name ( 1 ) pin type buffer type pps description an0-an21 an0alt-an1alt ii analog analog nono analog input channels. alternate analog input channels. clki clko i o st/ cmos nono external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1osc2 i i/o st/ cmos nono oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. refclko o yes reference clock output. ic1-ic4 i st yes capture inputs 1 through 4. ocfa oc1-oc4 i o st yes yes compare fault a input (for compare channels). compare outputs 1 through 4. int0 int1 int2 int4 ii i i stst st st no yes yes no external interrupt 0. external interrupt 1. external interrupt 2. external interrupt 4. ra0-ra4 i/o st no porta is a bidirectional i/o port. rb0-rb15 i/o st no portb is a bidirectional i/o port. rc0-rc15 i/o st no portc is a bidirectional i/o port. rd0-rd15 i/o st no portd is a bidirectional i/o port. t1ck t2ck t3ck t4ck t5ck ii i i i stst st st st yes yes yes nono timer1 external clock input. timer2 external clock input. timer3 external clock input. timer4 external clock input. timer5 external clock input. u1cts u1rts u1rx u1tx bclk1 i o i oo st st st yes yes yes yes yes uart1 clear-to-send. uart1 request-to-send. uart1 receive. uart1 transmit. uart1 irda ? baud clock output. u2cts u2rts u2rx u2tx bclk2 i o i oo st st st yes yes yes yes yes uart2 clear-to-send. uart2 request-to-send. uart2 receive. uart2 transmit. uart2 irda baud clock output. sck1 sdi1 sdo1 ss1 i/o i o i/o stst st yes yes yes yes synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. sck2 sdi2 sdo2 ss2 i/o i o i/o stst st yes yes yes yes synchronous serial clock input/output for spi2. spi2 data in. spi2 data out. spi2 slave synchronization or frame pulse i/o. legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer 1: not all pins are available in all packages variants. see the pin diagrams section for pin availability. 2: these pins are dedicated on 64-pin devices. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 13 dspic33epxxgs50x family scl1 sda1 ascl1 asda1 i/o i/o i/o i/o stst st st nono no no synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/output for i2c1. alternate synchronous serial data input/output for i2c1. scl2 sda2 ascl2 asda2 i/o i/o i/o i/o stst st st nono no no synchronous serial clock input/output for i2c2. synchronous serial data input/output for i2c2. alternate synchronous serial clock input/output for i2c2. alternate synchronous serial data input/output for i2c2. tms tck tdi tdo ii i o stst st nono no no jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. flt1-flt8 flt9-flt12 pwm1l-pwm3l pwm1h-pwm3h pwm4l-pwm5l ( 2 ) pwm4h-pwm5h ( 2 ) synci1, synci2 synco1, synco2 ii oo o o i o stst st yes nono no yes yes yes yes pwm fault inputs 1 through 8. pwm fault inputs 9 through 12. pwm low outputs 1 through 3. pwm high outputs 1 through 3. pwm low outputs 4 and 5. pwm high outputs 4 and 5. pwm synchronization inputs 1 and 2. pwm synchronization outputs 1 and 2. cmp1a-cmp4a cmp1b-cmp4b cmp1c-cmp4c cmp1d-cmp4d ii i i analog analog analog analog nono no no comparator channels 1 through 4 a input. comparator channels 1 through 4 b input. comparator channels 1 through 4 c input. comparator channels 1 through 4 d input. dacout1, dacout2 o no dac output voltages 1 and 2. extref1, extref2 i analog no external voltage reference inputs 1 and 2 for the reference dacs. isrc1-isrc4 o analog no constant-current outputs 1 through 4. pga1p1-pga1p4 i analog no pga1 positive inputs 1 through 4. pga1n1-pga1n3 i analog no pga1 negative inputs 1 through 3. pga2p1-pga2p4 i analog no pga2 positive inputs 1 through 4. pga2n1-pga2n3 i analog no pga2 negative inputs 1 through 3. adtrg31 i st no external adc trigger source. pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i stst st st st st nono no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. table 1-1: pinout i/o descriptions (continued) pin name ( 1 ) pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer 1: not all pins are available in all packages variants. see the pin diagrams section for pin availability. 2: these pins are dedicated on 64-pin devices. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 14 ? 2013-2015 microchip technology inc. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. av dd p p no positive supply for analog modules. this pin must be connected at all times. av ss p p no ground reference for analog modules. this pin must be connected at all times. v dd p no positive supply for peripheral logic and i/o pins. v cap p no cpu logic filter capacitor connection. v ss p no ground reference for logic and i/o pins. table 1-1: pinout i/o descriptions (continued) pin name ( 1 ) pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer 1: not all pins are available in all packages variants. see the pin diagrams section for pin availability. 2: these pins are dedicated on 64-pin devices. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 15 dspic33epxxgs50x family 2.0 guidelines for getting started with 16-bit digital signal controllers 2.1 basic connection requirements getting started with the dspic33epxxgs50x family requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names which must always be connected: all v dd and v ss pins (see section 2.2 decoupling capacitors ) all av dd and av ss pins regardless if adc module is not used (see section 2.2 decoupling capacitors ) v cap (see section 2.3 cpu logic filter capacitor connection (v cap ) ) mclr pin (see section 2.4 master clear (mclr) pin ) pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 icsp pins ) osc1 and osc2 pins when external oscillator source is used (see section 2.6 external oscillator pins ) 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss is required. consider the following criteria when using decoupling capacitors: value and type of capacitor: recommendation of 0.1 f (100 nf), 10-20v. this capacitor should be a low-esr and have resonance frequency in the range of 20 mhz and higher. it is recommended to use ceramic capacitors. placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. handling high-frequency noise: if the board is experiencing high-frequency noise, above tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb track inductance. note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 16 ? 2013-2015 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply source to the device and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 cpu logic filter capacitor connection (v cap ) a low-esr (<0.5 ? ) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd and must have a capacitor greater than 4.7 f (10 f is recommended), 16v connected to ground. the type can be ceramic or tantalum. see section 26.0 electrical characteristics for additional information. the placement of this capacitor should be close to the v cap pin. it is recommended that the trace length not exceeds one-quarter inch (6 mm). see section 23.4 on-chip voltage regulator for details. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset device programming and debugging. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that the capacitor c, be isolated from the mclr pin during programming and debugging operations. place the components as shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections note 1: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 ? and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 ? lc ?? ----------------------- = l 1 2 ? fc ?? --------------------- - ?? ?? 2 = (i.e., adc conversion rate/2) dspic33ep v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (1) r1 10 f tantalum c r1 (2) r (1) v dd mclr dspic33ep jp note 1: r ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r1 ? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 17 dspic33epxxgs50x family 2.5 icsp pins the pgecx and pgedx pins are used for icsp and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp con- nector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin voltage input high (v ih ) and voltage input low (v il ) requirements. ensure that the communication channel select (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to mplab ? pickit? 3, mplab icd 3, or mplab real ice?. for more information on mplab icd 2, mplab icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. using mplab ? icd 3 (poster) ds51765 multi-tool design advisory ds51764 mplab ? real ice? in-circuit emulator users guide ds51616 using mplab ? real ice? in-circuit emulator (poster) ds51749 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. for details, see section 8.0 oscillator configuration for details. the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is shown in figure 2-3 . figure 2-3: suggested placement of the oscillator circuit main oscillator guard ring guard trace oscillator pins downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 18 ? 2013-2015 microchip technology inc. 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 3 mhz < f in < 5.5 mhz to comply with device pll start-up conditions. this means that if the external oscillator frequency is outside this range, the application must start-up in the frc mode first. the default pll settings after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can initialize the pll sfrs, clkdiv and plldbf to a suitable value, and then perform a clock switch to the oscillator + pll clock source. note that clock switching must be enabled in the device configuration word. 2.8 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternatively, connect a 1k to 10k resistor between v ss and unused pins and drive the output to logic low. 2.9 targeted applications power factor correction (pfc) - interleaved pfc - critical conduction pfc - bridgeless pfc dc/dc converters - buck, boost, forward, flyback, push-pull - half/full-bridge - phase-shift full-bridge - resonant converters dc/ac - half/full-bridge inverter - resonant inverter examples of typical application connections are shown in figure 2-4 through figure 2-6 . figure 2-4: interleaved pfc v ac v out + pga/adc channel pwm adc pwm |v ac | k 4 k 3 fet dspic33epxxgs50x driver v out - adc channel pga/adc channel channel pga/adc channel k 2 fet driver k 1 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 19 dspic33epxxgs50x family figure 2-5: phase-shifte d full-bridge converter v in + v in - s1 gate 4 gate 2 gate 3 gate 1 analog ground v out + v out - k 2 fet driver k 1 fet driver fet driver gate 1 gate 2 s1 gate 3 gate 4 s3 s3 gate 6 gate 5 gate 6 gate 5 dspic33epxxgs50x pwm pwm pga/adc channel pwm adc channel downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 20 ? 2013-2015 microchip technology inc. figure 2-6: off-line ups pga/adc adc adc adc adc pwm pwm pwm dspic33epxxgs50x pwm pwm pwm fet driver k 2 k 1 fet driver fet driver fet driver fet driver k 4 k 5 v bat gnd + v out + v out - full-bridge inverter push-pull converter v dc gnd fet driver adc pwm k 3 k 6 or analog comp. battery charger + fet driver downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 21 dspic33epxxgs50x family 3.0 cpu the dspic33epxxgs50x family cpu has a 16-bit (data) modified harvard architecture with an enhanced instruction set, including significant support for digital signal processing (dsp). the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory space. an instruction prefetch mechanism helps maintain throughput and provides predictable execution. most instructions execute in a single-cycle effective execu- tion rate, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction, psv accesses and the table instructions. overhead-free program loop constructs are supported using the do and repeat instructions, both of which are interruptible at any point. 3.1 registers the dspic33epxxgs50x devic es have sixteen, 16-bit working registers in the programmers model. each of the working registers can act as a data, address or address offset register. the 16th working register (w15) operates as a software stack pointer for interrupts and calls. in addition, the dspic33epxxgs50x devices include two alternate working register sets which consist of w0 through w14. the alternate registers can be made per- sistent to help reduce the saving and restoring of register content during interrupt service routines (isrs). the alternate working registers can be assigned to a specific interrupt priority level (ipl1 through ipl6) by configuring the ctxtx<2:0> bits in the faltreg configuration register. the alternate working registers can also be accessed manually by using the ctxtswp instruction. the cctxi<2:0> and mctxi<2:0> bits in the ctxtstat register can be used to identify the current and most recent, manually selected working register sets. 3.2 instruction set the instruction set for dspic33epxxgs50x devices has two classes of instructions: the mcu class of instructions and the dsp class of instructions. these two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. the instruction set includes many addressing modes and was designed for optimum c compiler efficiency. 3.3 data space addressing the base data space can be addressed as up to 4k words or 8 kbytes, and is split into two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operates solely through the x memory agu, which accesses the entire memory map as one linear data space. certain dsp instructions operate through the x and y agus to sup- port dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device-specific. the upper 32 kbytes of the data space memory map can optionally be mapped into program space (ps) at any 16k program word boundary. the program-to-data space mapping feature, known as program space visibility (psv), lets any instruction access program space as if it were data space. refer to data memory (ds70595) in the dspic33/pic24 family reference manual for more details on psv and table accesses. on dspic33epxxgs50x devices, overhead-free circular buffers (modulo addressing) are supported in both x and y address spaces. the modulo addressing removes the software boundary checking overhead for dsp algorithms. the x agu circular addressing can be used with any of the mcu class of instructions. the x agu also supports bit-reversed addressing to greatly simplify input or output data re-ordering for radix-2 fft algorithms. 3.4 addressing modes the cpu supports these addressing modes: inherent (no operand) relative literal memory direct register direct register indirect each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. as many as six addressing modes are supported for each instruction. note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to cpu (ds70359) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 22 ? 2013-2015 microchip technology inc. figure 3-1: dspic33epxxgs50x family cpu block diagram instruction decode and control 16 pcl 16 program counter 16-bit alu 24 24 24 24 x data bus pcu 16 16 16 divide support engine dsp rom latch 16 y data bus ea mux x ragu x wagu y agu 16 24 16 16 16 16 16 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch data latch y data ram x data ram address latch address latch 16 data latch 16 16 16 x address bus y address bus 24 literal data program memory address latch power, reset and oscillator control signals to various blocks ports peripheral modules modules pch ir 16-bit working register arrays downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 23 dspic33epxxgs50x family 3.5 programmers model the programmers model for the dspic33epxxgs50x family is shown in figure 3-2 . all registers in the programmers model are memory-mapped and can be manipulated directly by instructions. table 3-1 lists a description of each register. in addition to the registers contained in the programmers model, the dspic33epxxgs50x devices contain control registers for modulo addressing, bit-reversed addressing and interrupts. these registers are described in subsequent sections of this document. all registers associated with the programmers model are memory-mapped, as shown in table 3-1 . table 3-1: programmers model register descriptions register(s) name description w0 through w15 ( 1 ) working register array w0 through w14 ( 1 ) alternate 1 working register array w0 through w14 ( 1 ) alternate 2 working register array acca, accb 40-bit dsp accumulators pc 23-bit program counter sr alu and dsp engine status register splim stack pointer limit value register tblpag table memory page address register dsrpag extended data space (eds) read page register rcount repeat loop counter register dcount do loop counter register dostarth ( 2 ) , dostartl ( 2 ) do loop start address register (high and low) doendh, doendl do loop end address register (high and low) corcon contains dsp engine, do loop control and trap status bits note 1: memory-mapped w0 through w14 represent the value of the register in the currently active cpu context. 2: the dostarth and dostartl registers are read-only. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 24 ? 2013-2015 microchip technology inc. figure 3-2: programmers model novz c tblpag pc23 pc0 7 0 d0 d15 program counter data table page address status register working/address registers dsp operand registers w0 (wreg) w1w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 frame pointer/w14 stack pointer/w15 dsp address registers ad39 ad0 ad31 dsp accumulators (1) acca accb dsrpag 9 0 ra 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter and stack dostart 23 0 do loop start address and stack 0 doend do loop end address and stack ipl2 ipl1 splim stack pointer limit ad15 23 0 srl ipl0 push.s and pop.s shadows nested do stack 0 0 oab sab x data space read page address da dc 0 0 00 corcon 15 0 cpu core control register w0-w3 d15 d0 w0 w1 w2 w3w4 w13 w14 w12 w11 w10 w9 w5 w6w7 w8 w0 w1 w2 w3w4 w13 w14 w12 w9 w5 w6w7 w8 w10 w11 d0 alternate working/address registers d15 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 25 dspic33epxxgs50x family 3.6 cpu resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 3.6.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 26 ? 2013-2015 microchip technology inc. 3.7 cpu control registers register 3-1: sr: cpu status register r/w-0 r/w-0 r/w-0 r/w-0 r/c-0 r/c-0 r-0 r/w-0 oa ob sa ( 3 ) sb ( 3 ) oab sab da dc bit 15 bit 8 r/w-0 ( 2 ) r/w-0 ( 2 ) r/w-0 ( 2 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 1 ) ipl1 ( 1 ) ipl0 ( 1 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1= bit is set 0 = bit is cleared x = bit is unknown bit 15 oa: accumulator a overflow status bit 1 = accumulator a has overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit 1 = accumulator b has overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation sticky status bit ( 3 ) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation sticky status bit ( 3 ) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumulator overflow status bit 1 = accumulators a or b have overflowed 0 = neither accumulators a or b have overflowed bit 10 sab: sa || sb combined accumulator sticky status bit 1 = accumulators a or b are saturated or have been saturated at some time 0 = neither accumulator a or b are saturated bit 9 da: do loop active bit 1 = do loop in progress 0 = do loop not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred note 1: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 2: the ipl<2:0> status bits are read-only when the nstdis bit (intcon1<15>) = 1 . 3: a data write to the sr register can modify the sa and sb bits by either a data write to sa and sb or by clearing the sab bit. to avoid a possible sa or sb bit write race condition, the sa and sb bits should not be modified using bit operations. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 27 dspic33epxxgs50x family bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 1 , 2 ) 111 = cpu interrupt priority level is 7 (15); user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop is in progress 0 = repeat loop is not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2s complement). it indicates an overflow of the magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 2: the ipl<2:0> status bits are read-only when the nstdis bit (intcon1<15>) = 1 . 3: a data write to the sr register can modify the sa and sb bits by either a data write to sa and sb or by clearing the sab bit. to avoid a possible sa or sb bit write race condition, the sa and sb bits should not be modified using bit operations. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 28 ? 2013-2015 microchip technology inc. register 3-2: corcon: core control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 var us1 us0 edt ( 1 ) dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) sfa rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 var: variable exception processing latency control bit 1 = variable exception processing is enabled 0 = fixed exception processing is enabled bit 14 unimplemented: read as 0 bit 13-12 us<1:0>: dsp multiply unsigned/signed control bits 11 = reserved 10 = dsp engine multiplies are mixed-sign 01 = dsp engine multiplies are unsigned 00 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit ( 1 ) 1 = terminates executing do loop at the end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops are active 001 = 1 do loop is active 000 = 0 do loops are active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation is enabled 0 = accumulator a saturation is disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation is enabled 0 = accumulator b saturation is disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation is enabled 0 = data space write saturation is disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: this bit is always read as 0 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 29 dspic33epxxgs50x family bit 2 sfa: stack frame active status bit 1 = stack frame is active; w14 and w15 address 0x0000 to 0xffff, regardless of dsrpag 0 = stack frame is not active; w14 and w15 address the base data space bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding is enabled 0 = unbiased (convergent) rounding is enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode is enabled for dsp multiply 0 = fractional mode is enabled for dsp multiply register 3-2: corcon: core control register (continued) note 1: this bit is always read as 0 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. register 3-3: ctxtstat: cpu w re gister context status register u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 cctxi2 cctxi1 cctxi0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 mctxi2 mctxi1 mctxi0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 cctxi<2:0>: current (w register) context identifier bits 111 = reserved 011 = reserved 010 = alternate working register set 2 is currently in use 001 = alternate working register set 1 is currently in use 000 = default register set is currently in use bit 7-3 unimplemented: read as 0 bit 2-0 mctxi<2:0>: manual (w register) context identifier bits 111 = reserved 011 = reserved 010 = alternate working register set 2 was most recently manually selected 001 = alternate working register set 1 was most recently manually selected 000 = default register set was most recently manually selected downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 30 ? 2013-2015 microchip technology inc. 3.8 arithmetic logic unit (alu) the dspic33epxxgs50x family alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are twos complement in nature. depending on the operation, the alu can affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. refer to the 16-bit mcu and dsc programmers reference manual (ds70157) for information on the sr bits affected by each instruction. the core cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 3.8.1 multiplier using the high-speed 17-bit x 17-bit multiplier, the alu supports unsigned, signed, or mixed-sign operation in several mcu multiplication modes: 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit signed x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.8.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.9 dsp engine the dsp engine consists of a high-speed 17-bit x 17-bit multiplier, a 40-bit barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). the dsp engine can also perform inherent accumulator- to-accumulator operations that require no additional data. these instructions are, add , sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: fractional or integer dsp multiply (if) signed, unsigned or mixed-sign dsp multiply (usx) conventional or convergent rounding (rnd) automatic saturation on/off for acca (sata) automatic saturation on/off for accb (satb) automatic saturation on/off for writes to data memory (satdw) accumulator saturation mode selection (accsat) table 3-2: dsp instructions summary instruction algebraic operation acc write-back clr a = 0 yes ed a = (x C y) 2 no edac a = a + (x C y) 2 no mac a = a + (x y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x y no mpy a = x 2 no mpy.n a = C x y no msc a = a C x y yes downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 31 dspic33epxxgs50x family 4.0 memory organization the dspic33epxxgs50x family architecture features separate program and data memory spaces, and buses. this architecture also allows the direct access of program memory from the data space (ds) during code execution. 4.1 program address space the program address memory space of the dspic33epxxgs50x family devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit pc during program execution, or from table operation or data space remapping, as described in section 4.9 interfacing program and data memory spaces . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd operations, which use tblpag<7> to permit access to calibration data and device id sections of the configuration memory space. the program memory maps for the dspic33ep16/ 32gs50x and dspic33ep64gs50x devices not operating in dual partition mode, are shown in figure 4-1 through figure 4-3 . the dspic33ep64gs50x devices can operate in a dual partition flash program memory mode, where the user program flash memory is arranged as two separate address spaces, one for each of the flash partitions. the active partition always starts at address, 0x000000, and contains half of the avail- able flash memory (32k). the inactive partition always starts at address, 0x400000, and implements the remaining half of flash memory. as shown in figure 4-4 , the active and inactive partitions are identical and both contain unique copies of the reset vector, interrupt vector tables (ivt and aivt if enabled) and the flash configuration words. 4.2 unique device identifier (udid) all (16-bit devices) family devices are individually encoded during final manufacturing with a unique device identifier or udid. this feature allows for manufacturing traceability of microchip technology devices in applications where this is a requirement. it may also be used by the application manufacturer for any number of things that may require unique identification, such as: tracking the device unique serial number unique security key the udid comprises five 24-bit program words. when taken together, these fields form a unique 120-bit identifier. the udid is stored in five read-only locations, located between 800f00h and 800f08h in the device configuration space. table 4-1 lists the addresses of the identifier words and shows their contents. table 4-1: udid addresses note: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to dspic33e/pic24e program memory (ds70000613) in the dspic33/ pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). name address bits 23:16 bits 15:8 bits 7:0 udid1 800f00 udid word 1 udid2 800f02 udid word 2 udid3 800f04 udid word 3 udid4 800f06 udid word 4 udid5 800f08 udid word 5 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 32 ? 2013-2015 microchip technology inc. figure 4-1: program memory map for dspic33ep16gs50x devices reset address 0x000000 0x000002 write latches user program flash memory 0x002b80 0x002b7e (5312 instructions) 0x800000 0xfa0000 0xfa0002 0xfa0004 devid 0xfefffe 0xff0000 0xfffffe 0xf9fffe unimplemented (read 0 s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe interrupt vector table configuration memory space user memory space device configuration 0x002c00 0x002bfe reserved 0xff0002 note: memory areas are not shown to scale. 0xff0004 0x800e48 0x800e46 0x801000 0x800ffc reserved calibration data reserved user otp memory 0x800e7a 0x800e78 0x800f80 0x800f7e downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 33 dspic33epxxgs50x family figure 4-2: program memory map for dspic33ep32gs50x devices reset address 0x000000 0x000002 write latches user program flash memory 0x005780 0x00577e (10,944 instructions) 0x800000 0xfa0000 0xfa0002 0xfa0004 devid 0xfefffe 0xff0000 0xfffffe 0xf9fffe unimplemented (read 0 s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe interrupt vector table configuration memory space user memory space device configuration 0x005800 0x0057fe reserved 0xff0002 note: memory areas are not shown to scale. 0xff0004 reserved 0x800f80 0x800f7e 0x801000 0x800ffc user otp memory reserved calibration data 0x800e7a 0x800e78 0x800e48 0x800e46 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 34 ? 2013-2015 microchip technology inc. figure 4-3: program memory map for dspic33ep64gs50x devices reset address 0x000000 0x000002 write latches user program flash memory 0x00af80 0x00af7e (22,207 instructions) 0xfa0000 0xfa0002 0xfa0004 devid 0xfefffe 0xff0000 0xfffffe 0xf9fffe unimplemented (read 0 s) goto instruction 0x000004 reserved reserved 0x000200 0x0001fe interrupt vector table configuration memory space user memory space device configuration 0x00b000 0x00affe reserved 0xff0002 note: memory areas are not shown to scale. 0xff0004 0x800000 0x7ffffe reserved 0x800f80 0x800f7e user otp memory reserved calibration data 0x800e7a 0x800e78 0x800e48 0x800e46 0x801000 0x800ffc downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 35 dspic33epxxgs50x family figure 4-4: program memory map for dspic33ep64gs50x devices (dual partition) reset address 0x000000 0x000002 write latches active program flash memory 0x005780 0x00577e (10,944 instructions) 0xfa0000 0xfa0002 0xfa0004 devid 0xfefffe 0xff0000 0xfffffe 0xf9fffe goto instruction 0x000004 reserved reserved 0x000200 0x0001fe interrupt vector table configuration memory space user memory space device configuration 0x005800 0x0057fe reserved 0xff0002 note: memory areas are not shown to scale. 0xff0004 unimplemented (read 0 s) flash memory (10,944 instructions) inactive program device configuration unimplemented (read 0 s) 0x400000 0x3ffffe 0x405800 0x4057fe 0x405780 0x40577e user otp memory reserved 0x800000 0x7ffffe calibration data 0x800e48 0x800e46 reserved 0x800100 0x800ffc 0x800e7a 0x800e78 0x800f80 0x800f7e goto instruction reset address interrupt vector table 0x400002 0x400200 0x400004 0x4001fe active partition inactive partition downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 36 ? 2013-2015 microchip technology inc. 4.2.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address ( figure 4-5 ). program memory addresses are always word-aligned on the lower word, and addresses are incremented, or decremented, by two, during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.2.2 interrupt and trap vectors all dspic33epxxgs50x family devices reserve the addresses between 0x000000 and 0x000200 for hard- coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at address, 0x000000, of flash memory, with the actual address for the start of code at address, 0x000002, of flash memory. a more detailed discussion of the interrupt vector tables (ivts) is provided in section 7.1 interrupt vector table . figure 4-5: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 0000000000000000 00000000 00000000 program memory phantom byte (read as 0 ) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 37 dspic33epxxgs50x family 4.3 data address space the dspic33epxxgs50x family cpu has a separate 16-bit wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps are shown in figure 4-6 through figure 4-8 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a base data space address range of 64 kbytes or 32k words. the lower half of the data memory space (i.e., when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility (psv). dspic33epxxgs50x family devices implement up to 12 kbytes of data memory. if an ea points to a location outside of this area, an all-zero word or byte is returned. 4.3.1 data space width the data memory space is organized in byte- addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.3.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic33epxxgs50x family instruc- tion set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word- aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] results in a value of ws + 1 for byte operations and ws + 2 for word operations. a data byte read, reads the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. data byte writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the error occurred on a read, the instruction underway is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the lsb; the msb is not modified. a sign-extend ( se ) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.3.3 sfr space the first 4 kbytes of the near data space, from 0x0000 to 0x0fff, is primarily occupied by special function registers (sfrs). these are used by the dspic33epxxgs50x family core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as 0 . 4.3.4 near data space the 8-kbyte area, between 0x0000 and 0x1fff, is referred to as the near data space. locations in this space are directly addressable through a 13-bit absolute address field within all memory direct instructions. addi- tionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field, or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 38 ? 2013-2015 microchip technology inc. figure 4-6: data memory map fo r dspic33ep16gs50x devices 0x0000 0x0ffe 0x13fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x0fff 0x13ff 0xffff optionally mapped into program memory 0x17ff 0x17fe 0x1001 0x1000 0x1401 0x1400 4-kbyte sfr space 2-kbyte sram space 0x1800 0x1801 data space near 8-kbyte sfr space x data ram (x) x data unimplemented (x) 0x8000 0x8001 note: memory areas are not shown to scale. y data ram (y) 0x1fff 0x2001 0x1ffe 0x2000 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 39 dspic33epxxgs50x family figure 4-7: data memory map for dspic33ep32gs50x devices 0x0000 0x0ffe 0x17fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x0fff 0x17ff 0xffff optionally mapped into program memory 0x1fff 0x1ffe 0x1001 0x1000 0x1801 0x1800 4-kbyte sfr space 4-kbyte sram space 0x2000 0x2001 data space near 8-kbyte sfr space x data ram (x) x data unimplemented (x) 0x8000 0x8001 note: memory areas are not shown to scale. y data ram (y) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 40 ? 2013-2015 microchip technology inc. figure 4-8: data memory map for dspic33ep64gs50x devices 0x0000 0x0ffe 0x1ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x0fff 0x1fff 0xffff optionally mapped into program memory 0x2fff 0x2ffe 0x1001 0x1000 0x2001 0x2000 4-kbyte sfr space 8-kbyte sram space 0x3000 0x3001 data space near 8-kbyte sfr space x data ram (x) x data unimplemented (x) 0x8000 0x8001 note: memory areas are not shown to scale. y data ram (y) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 41 dspic33epxxgs50x family 4.3.5 x and y data spaces the dspic33epxxgs50x core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions) or as one unified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient execution of dsp algorithms, such as finite impulse response (fir) filtering and fast fourier transform (fft). the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch path for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr , ed , edac , mac , movsac , mpy , mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo address- ing mode for all instructions, subject to addressing mode restrictions. bit-reversed addressing mode is only supported for writes to x data space. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. 4.4 memory resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 4.4.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 42 ? 2013-2015 microchip technology inc. 4.5 special function register maps table 4-2: cpu core register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets w0 0000 w0 (wreg) xxxx w1 0002 w1 xxxx w2 0004 w2 xxxx w3 0006 w3 xxxx w4 0008 w4 xxxx w5 000a w5 xxxx w6 000c w6 xxxx w7 000e w7 xxxx w8 0010 w8 xxxx w9 0012 w9 xxxx w10 0014 w10 xxxx w11 0016 w11 xxxx w12 0018 w12 xxxx w13 001a w13 xxxx w14 001c w14 xxxx w15 001e w15 xxxx splim 0020 splim 0000 accal 0022 accal 0000 accah 0024 accah 0000 accau 0026 sign extension of acca<39> accau 0000 accbl 0028 accbl 0000 accbh 002a accbh 0000 accbu 002c sign extension of accb<39> accbu 0000 pcl 002e pcl<15:1> 0000 pch 0030 pch<6:0> 0000 dsrpag 0032 extended data space (eds) read page register (dsrpag<9:0>) 0001 dswpag ( 1 ) 0034 extended data space (eds) write page register (dswpag8:0>) ( 1 ) 0001 rcount 0036 rcount<15:0> 0000 dcount 0038 do loop count register (dcount<15:0>) 0000 dostartl 003a do start address register low (dostartl<15:1>) 0000 dostarth 003c do start address register high (dostarth<5:0>) 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: the contents of this register should never be modified. the dswpag must always point to the first page. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 43 dspic33epxxgs50x family doendl 003e do loop end address register low (doendl<15:1>) 0000 doendh 0040 do loop end address register high (doendh<5:0>) 0000 sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 var us1 us0 edt dl2 dl1 dl0 sata satb satdw accsat ipl3 sfa rnd if 0020 modcon 0046 xmoden ymoden bwm3 bwm2 bwm1 bwm0 ywm3 ywm2 ywm1 ywm0 xwm3 xwm2 xwm1 xwm0 0000 xmodsrt 0048 x mode start address register (xmodsrt<15:1>) 0000 xmodend 004a x mode end address register (xmodend<15:1>) 0001 ymodsrt 004c y mode start address register (ymodsrt<15:1>) 0000 ymodend 004e y mode end address register (ymodend<15:1>) 0001 xbrev 0050 bren xbrev<14:0> 0000 disicnt 0052 disicnt<13:0> 0000 tblpag 0054 t b l p a g < 7 : 0 > 0000 ctxtstat 005a cctxi2 cctxi1 cctxi0 mctxi2 mctxi1 mctxi0 0000 table 4-2: cpu core register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: the contents of this register should never be modified. the dswpag must always point to the first page. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 44 ? 2013-2015 microchip technology inc. table 4-3: interrupt controller register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif adcif u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if int1if cnif ac1if mi2c1if si2c1if 0000 ifs2 0804 ic4if ic3if spi2if spi2eif 0000 ifs3 0806 psemif i n t 4 i f mi2c2if si2c2if 0000 ifs4 0808 psesif u 2 e i fu 1 e i f 0000 ifs5 080a pwm2if pwm1if 0000 ifs6 080c adcan1if adcan0if a c 4 i fa c 3 i fa c 2 i f pwm5if pwm4if pwm3if 0000 ifs7 080e adcan7if adcan6if adcan5if adcan4if adcan3if adcan2if 0000 ifs8 0810 jtagif icdif 0000 ifs9 0812 adcan16if ( 1 ) adcan15if ( 1 ) adcan14if ( 2 ) adcan13if ( 1 ) adcan12if ( 2 ) adcan11if ( 2 ) adcan10if ( 2 ) adcan9if ( 2 ) adcan8if ( 2 ) 0000 ifs10 0814 i2c2bcif i2c1bcif adcan21if adcan20if adcan19if adcan18if adcan17if ( 2 ) 0000 ifs11 0816 adfltr1if adfltr0if adcmp1if adcmp0if 0000 iec0 0820 nvmie adcie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie int1ie cnie ac1if mi2c1ie si2c1ie 0000 iec2 0824 ic4ie ic3ie spi2ie spi2eie 0000 iec3 0826 p s e m i e i n t 4 i e mi2c2ie si2c2ie 0000 iec4 0828 psesie u 2 e i eu 1 e i e 0000 iec5 082a pwm2ie pwm1ie 0000 iec6 082c adcan1ie adcan0ie a c 4 i ea c 3 i ea c 2 i e pwm5ie pwm4ie pwm3ie 0000 iec7 082e adcan7ie adcan6ie adcan5ie adcan4ie adcan3ie adcan2ie 0000 iec8 0830 jtagie icdie 0000 iec9 0832 adcan16ie ( 1 ) adcan15ie ( 1 ) adcan14ie ( 2 ) adcan13ie ( 1 ) adcan12ie ( 2 ) adcan11ie ( 2 ) adcan10ie ( 2 ) adcan9ie ( 2 ) adcan8ie ( 2 ) 0000 iec10 0834 i2c2bcie i2c1bcie adcan21ie adcan20ie adcan19ie adcan18ie adcan17ie ( 2 ) 0000 iec11 0836 adfltr1ie adfltr0ie adcmp1ie adcmp0ie 0000 ipc0 0840 t1ip2 t1ip1 t1ip0 oc1ip2 oc1ip1 oc1ip0 ic1ip2 ic1ip1 ic1ip0 int0ip2 int0ip1 int0ip0 4444 ipc1 0842 t2ip2 t2ip1 t2ip0 oc2ip2 oc2ip1 oc2ip0 ic2ip2 ic2ip1 ic2ip0 4440 ipc2 0844 u1rxip2 u1rxip1 u1rxip0 spi1ip2 spi1ip1 spi1ip0 spi1eip2 spi1eip1 spi1eip0 t3ip2 t3ip1 t3ip0 4444 ipc3 0846 nvmip2 nvmip1 nvmip0 adcip2 adcip1 adcip0 u1txip2 u1txip1 u1txip0 4044 ipc4 0848 cnip2 cnip1 cnip0 ac1ip2 ac1ip1 ac1ip0 mi2c1ip2 mi2c1ip1 mi2c1ip0 si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 084a int1ip2 int1ip1 int1ip0 0004 ipc6 084c t4ip2 t4ip1 t4ip0 oc4ip2 oc4ip1 oc4ip0 oc3ip2 oc3ip1 oc3ip0 4440 ipc7 084e u2txip2 u2txip1 u2txip0 u2rxip2 u2rxip1 u2rxip0 int2ip2 int2ip1 int2ip0 t5ip2 t5ip1 t5ip0 4444 ipc8 0850 spi2ip2 spi2ip1 spi2ip0 spi2eip2 spi2eip1 spi2eip0 0044 ipc9 0852 ic4ip2 ic4ip1 ic4ip0 ic3ip2 ic3ip1 ic3ip0 0440 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: only available on dspic33epxxgs506 devices. 2: only available on dspic33epxxgs504/505 and dspic33epxxgs506 devices. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 45 dspic33epxxgs50x family ipc12 0858 mi2c2ip2 mi2c2ip1 mi2c2ip0 si2c2ip2 si2c2ip1 si2c2ip0 0440 ipc13 085a int4ip2 int4ip1 int4ip0 0400 ipc14 085c psemip2 psemip1 psemip0 0040 ipc16 0860 u2eip2 u2eip1 u2eip0 u1eip2 u1eip1 u1eip0 0440 ipc18 0864 psesip2 psesip1 psesip0 0040 ipc23 086e pwm2ip2 pwm2ip1 pwm2ip0 pwm1ip2 pwm1ip1 pwm1ip0 4400 ipc24 0870 pwm5ip2 pwm5ip1 pwm5ip0 pwm4ip2 pwm4ip1 pwm4ip0 pwm3ip2 pwm3ip1 pwm3ip0 0444 ipc25 0872 ac2ip2 ac2ip1 ac2ip0 4000 ipc26 0874 ac4ip2 ac4ip1 ac4ip0 ac3ip2 ac3ip1 ac3ip0 0044 ipc27 0876 adcan1ip2 adcan1ip1 adcan1ip0 adcan0ip2 adcan0ip1 adcan0ip0 4400 ipc28 0878 adcan5ip2 adcan5ip1 adcan5ip0 adcan4ip2 adcan4ip1 adcan4ip0 adcan3ip2 adcan3ip1 adcan3ip0 adcan2ip2 adcan2ip1 adcan2ip0 4444 ipc29 087a adcan7ip2 adcan7ip1 adcan7ip0 adcan6ip2 adcan6ip1 adcan6ip0 0044 ipc35 0886 jtagip2 jtagi p1 jtagip0 icdip2 icdip1 icdip0 4400 ipc37 088a adcan8ip2 ( 2 ) adcan8ip1 ( 2 ) adcan8ip0 ( 2 ) 4000 ipc38 088c adcan12ip2 ( 2 ) adcan12ip1 ( 2 ) adcan12ip0 ( 2 ) a d c a n 1 1 i p 2 ( 2 ) adcan11ip1 ( 2 ) adcan11ip0 ( 2 ) a d c a n 1 0 i p 2 ( 2 ) adcan10ip1 ( 2 ) adcan10ip0 ( 2 ) adcan9ip2 ( 2 ) adcan9ip1 ( 2 ) adcan9ip0 ( 2 ) 4444 ipc39 088e adcan16ip2 ( 1 ) adcan16ip1 ( 1 ) adcan16ip0 ( 1 ) adcan15ip2 ( 1 ) adcan15ip1 ( 1 ) adcan15ip0 ( 1 ) a d c a n 1 4 i p 2 ( 2 ) adcan14ip1 ( 2 ) adcan14ip0 ( 2 ) a d c a n 1 3 i p 2 ( 1 ) adcan13ip1 adcan13ip0 4444 ipc40 0890 adcan20ip2 adcan20ip1 adcan20ip0 adcan19ip2 adcan19ip1 adcan19ip0 adcan18ip2 adcan18ip1 adcan18ip0 a d c a n 1 7 i p 2 ( 2 ) adcan17ip1 ( 2 ) adcan17ip0 ( 2 ) 4444 ipc41 0892 adcan21ip2 adcan21ip1 adcan21ip0 0004 ipc43 0896 i2c2bcip2 i2c2bcip1 i2c2bcip0 i2c1bcip2 i2c1bcip1 i2c1bcip0 0440 ipc44 0898 adfltr0ip2 adfltr0ip1 adfltr0ip0 adcmp1ip2 adcmp1ip1 adcmp1ip0 adcmp0ip2 adcmp0ip1 adcmp0ip0 4440 ipc45 089a adfltr1ip2 adfltr1ip1 adfltr1ip0 0004 intcon1 08c0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err matherr addrerr stkerr oscfail 0000 intcon2 08c2 gie disi swtrap a i v t e n i n t 4 e p int2ep int1ep int0ep 8000 intcon3 08c4 n a e doovr a p l l 0000 intcon4 08c6 s g h t 0000 inttreg 08c8 ilr3 ilr2 ilr1 ilr0 vecnum7 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 table 4-3: interrupt controller register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: only available on dspic33epxxgs506 devices. 2: only available on dspic33epxxgs504/505 and dspic33epxxgs506 devices. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 46 ? 2013-2015 microchip technology inc. table 4-4: timer1 through timer5 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 bit 0 all resets tmr1 0100 timer1 register xxxx pr1 0102 period register 1 ffff t1con 0104 ton t s i d l tgate tckps1 tckps0 tsync tcs 0000 tmr2 0106 timer2 register xxxx tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register xxxx pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton t s i d l tgate tckps1 tckps0 t32 t c s 0000 t3con 0112 ton t s i d l tgate tckps1 tckps0 t c s 0000 tmr4 0114 timer4 register xxxx tmr5hld 0116 timer5 holding register (for 32-bit operations only) xxxx tmr5 0118 timer5 register xxxx pr4 011a period register 4 ffff pr5 011c period register 5 ffff t4con 011e ton t s i d l tgate tckps1 tckps0 t32 t c s 0000 t5con 0120 ton t s i d l tgate tckps1 tckps0 t c s 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 47 dspic33epxxgs50x family table 4-5: input capture 1 through input capture 4 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1con1 0140 icsidl ictsel2 ictsel1 ictsel0 ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic1con2 0142 ic32 ictrig trigstat syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic1buf 0144 input capture 1 buffer register xxxx ic1tmr 0146 input capture 1 timer register 0000 ic2con1 0148 icsidl ictsel2 ictsel1 ictsel0 ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2con2 014a ic32 ictrig trigstat syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic2buf 014c input capture 2 buffer register xxxx ic2tmr 014e input capture 2 timer register 0000 ic3con1 0150 icsidl ictsel2 ictsel1 ictsel0 ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic3con2 0152 ic32 ictrig trigstat syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic3buf 0154 input capture 3 buffer register xxxx ic3tmr 0156 input capture 3 timer register 0000 ic4con1 0158 icsidl ictsel2 ictsel1 ictsel0 ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic4con2 015a ic32 ictrig trigstat syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic4buf 015c input capture 4 buffer register xxxx ic4tmr 015e input capture 4 timer register 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 48 ? 2013-2015 microchip technology inc. table 4-6: output compare 1 through output compare 4 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1con1 0900 ocsidl octsel2 octsel1 octsel0 e n f l t a ocflta trigmode ocm2 ocm1 ocm0 0000 oc1con2 0902 fltmd fltout flttrien ocinv oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc1rs 0904 output compare 1 secondary register xxxx oc1r 0906 output compare 1 register xxxx oc1tmr 0908 timer value 1 register xxxx oc2con1 090a ocsidl octsel2 octsel1 octsel0 e n f l t a ocflta trigmode ocm2 ocm1 ocm0 0000 oc2con2 090c fltmd fltout flttrien ocinv oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc2rs 090e output compare 2 secondary register xxxx oc2r 0910 output compare 2 register xxxx oc2tmr 0912 timer value 2 register xxxx oc3con1 0914 ocsidl octsel2 octsel1 octsel0 e n f l t a ocflta trigmode ocm2 ocm1 ocm0 0000 oc3con2 0916 fltmd fltout flttrien ocinv oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc3rs 0918 output compare 3 secondary register xxxx oc3r 091a output compare 3 register xxxx oc3tmr 091c timer value 3 register xxxx oc4con1 091e ocsidl octsel2 octsel1 octsel0 e n f l t a ocflta trigmode ocm2 ocm1 ocm0 0000 oc4con2 0920 fltmd fltout flttrien ocinv oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc4rs 0922 output compare 4 secondary register xxxx oc4r 0924 output compare 4 register xxxx oc4tmr 0926 timer value 4 register xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 49 dspic33epxxgs50x family table 4-7: pwm register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ptcon 0c00 pten ptsidl sestat seien eipu syncpol syncoen syncen syncsrc2 syncsrc1 syncsrc0 sevtps3 sevtps2 sevtps1 sevtps0 0000 ptcon2 0c02 pclkdiv<2:0> 0000 ptper 0c04 pwmx primary master time base period register (ptper<15:0>) fff8 sevtcmp 0c06 pwmx special event compare register (sevtcmp12:0>) 0000 mdc 0c0a pwmx master duty cycle register (mdc<15:0>) 0000 stcon 0c0e sestat seien eipu syncpol syncoen syncen syncsrc2 syncsrc1 syncsrc0 sevtps3 sevtps2 sevtps1 sevtps0 0000 stcon2 0c10 pclkdiv<2:0> 0000 stper 0c12 pwmx secondary master time base period register (stper<15:0>) fff8 ssevtcmp 0c14 pwmx secondary special event compare register (ssevtcmp<12:0>) 0000 chop 0c1a chpclken chopclk6 chopclk5 chopclk4 chopclk3 chopclk2 chopclk1 chopclk0 0000 pwmkey 0c1e pwmx protection lock/unlock key register (pwmkey<15:0>) 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-8: pwm generator 1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 all resets pwmcon1 0c20 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 mtbs cam xpres iue 0000 iocon1 0c22 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 fltdat0 cldat1 cldat0 s wap osync c000 fclcon1 0c24 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 flts rc0 fltpol fltmod1 fltmod0 0000 pdc1 0c26 pwm1 generator duty cycle register (pdc1<15:0>) 0000 phase1 0c28 pwm1 primary phase-shift or independent time base period register (phase1<15:0>) 0000 dtr1 0c2a pwm1 dead-time register (dtr1<13:0>) 0000 altdtr1 0c2c pwm1 alternate dead-time register (altdtr1<13:0>) 0000 sdc1 0c2e pwm1 secondary duty cycle register (sdc1<15:0>) 0000 sphase1 0c30 pwm1 secondary phase-shift register (sphase1<15:0>) 0000 trig1 0c32 pwm1 primary trigger compare value register (trgcmp<12:0>) 0000 trgcon1 0c34 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig1 0c36 pwm1 secondary trigger compare value register (strgcmp<12:0>) 0000 pwmcap1 0c38 pwm1 primary time base capture register (pwmcap<12:0>) 0000 lebcon1 0c3a phr phf plr plf fltleben clleben bch bcl bphh bphl bplh bpll 0000 lebdly1 0c3c pwm1 leading-edge blanking delay register (leb<8:0>) 0000 auxcon1 0c3e hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 50 ? 2013-2015 microchip technology inc. table 4-9: pwm generator 2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon2 0c40 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 mtbs cam xpres iue 0000 iocon2 0c42 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 fltdat0 cldat1 cldat0 swap osync c000 fclcon2 0c44 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 f ltmod0 0000 pdc2 0c46 pwm2 generator duty cycle register (pdc2<15:0>) 0000 phase2 0c48 pwm2 primary phase-shift or independent time base period register (phase2<15:0>) 0000 dtr2 0c4a pwm2 dead-time register (dtr2<13:0>) 0000 altdtr2 0c4c pwm2 alternate dead-time register (altdtr2<13:0>) 0000 sdc2 0c4e pwm2 secondary duty cycle register (sdc2<15:0>) 0000 sphase2 0c50 pwm2 secondary phase-shift register (sphase2<15:0>) 0000 trig2 0c52 pwm2 primary trigger compare value register (trgcmp<12:0>) 0000 trgcon2 0c54 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig2 0c56 pwm2 secondary trigger compare value register (strgcmp<12:0>) 0000 pwmcap2 0c58 pwm2 primary time base capture register (pwmcap<12:0>) 0000 lebcon2 0c5a phr phf plr plf fltleben clleben bch bcl bphh bphl bplh bpll 0000 lebdly2 0c5c pwm2 leading-edge blanking delay register (leb<8:0>) 0000 auxcon2 0c5e hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-10: pwm generator 3 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon3 0c60 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 mtbs cam xpres iue 0000 iocon3 0c62 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 fltdat0 cldat1 cldat0 swap osync c000 fclcon3 0c64 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc3 0c66 pwm3 generator duty cycle register (pdc3<15:0>) 0000 phase3 0c68 pwm3 primary phase-shift or independent time base period register (phase3<15:0>) 0000 dtr3 0c6a pwm3 dead-time register (dtr3<13:0>) 0000 altdtr3 0c6c pwm3 alternate dead-time register (altdtr3<13:0>) 0000 sdc3 0c6e pwm3 secondary duty cycle register (sdc3<15:0>) 0000 sphase3 0c70 pwm3 secondary phase-shift register (sphase3<15:0>) 0000 trig3 0c72 pwm3 primary trigger compare value register (trgcmp<12:0>) 0000 trgcon3 0c74 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig3 0c76 pwm3 secondary trigger compare value register (strgcmp<12:0>) 0000 pwmcap3 0c78 pwm3 primary time base capture register (pwmcap<12:0>) 0000 lebcon3 0c7a phr phf plr plf fltleben clleben bch bcl bphh bphl bplh bpll 0000 lebdly3 0c7c pwm3 leading-edge blanking delay register (leb<8:0>) 0000 auxcon3 0c7e hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 51 dspic33epxxgs50x family table 4-11: pwm generator 4 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon4 0c80 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 mtbs cam xpres iue 0000 iocon4 0c82 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 fltdat0 cldat1 cldat0 swap osync c000 fclcon4 0c84 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 flt mod0 0000 pdc4 0c86 pwm4 generator duty cycle register (pdc4<15:0>) 0000 phase4 0c88 pwm4 primary phase-shift or independent time base period register (phase4<15:0>) 0000 dtr4 0c8a pwm4 dead-time register (dtr4<13:0>) 0000 altdtr4 0c8c pwm4 alternate dead-time register (altdtr4<13:0>) 0000 sdc4 0c8e pwm4 secondary duty cycle register (sdc4<15:0>) 0000 sphase4 0c90 pwm4 secondary phase-shift register (sphase4<15:0>) 0000 trig4 0c92 pwm4 primary trigger compare value register (trgcmp<12:0>) 0000 trgcon4 0c94 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig4 0c96 pwm4 secondary trigger compare value register (strgcmp<12:0>) 0000 pwmcap4 0c98 pwm4 primary time base capture register (pwmcap<12:0>) 0000 lebcon4 0c9a phr phf plr plf fltleben clleben bch bcl bphh bphl bplh bpll 0000 lebdly4 0c9c pwm4 leading-edge blanking delay register (leb<8:0>) 0000 auxcon4 0c9e hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-12: pwm generator 5 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon5 0ca0 fltstat clstat trgstat fltien clien trgien itb mdcs dtc1 dtc0 mtbs cam xpres iue 0000 iocon5 0ca2 penh penl polh poll pmod1 pmod0 ovrenh ovrenl ovrdat1 ovrdat0 fltdat1 fltdat0 cldat1 cldat0 swap osync c000 fclcon5 0ca4 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol clmod fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol fltmod1 fltmod0 0000 pdc5 0ca6 pwm5 generator duty cycle register (pdc5<15:0>) 0000 phase5 0ca8 pwm5 primary phase-shift or independent time base period register (phase5<15:0>) 0000 dtr5 0caa pwm5 dead-time register (dtr5<13:0>) 0000 altdtr5 0cac pwm5 alternate dead-time register (altdtr5<13:0>) 0000 sdc5 0cae pwm5 secondary duty cycle register (sdc5<15:0>) 0000 sphase5 0cb0 pwm5 secondary phase-shift register (sphase5<15:0>) 0000 trig5 0cb2 pwm5 primary trigger compare value register (trgcmp<12:0>) 0000 trgcon5 0cb4 trgdiv3 trgdiv2 trgdiv1 trgdiv0 d t m trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 0000 strig5 0cb6 pwm5 secondary trigger compare value register (strgcmp<12:0>) 0000 pwmcap5 0cb8 pwm5 primary time base capture register (pwmcap<12:0>) 0000 lebcon5 0cba phr phf plr plf fltleben clleben bch bcl bphh bphl bplh bpll 0000 lebdly5 0cbc pwm5 leading-edge blanking delay register (leb<8:0>) 0000 auxcon5 0cbe hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 52 ? 2013-2015 microchip technology inc. table 4-13: i2c1 and i2c2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1conl 0200 i2cen i2csidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1conh 0202 pcie scie boen sdaht sbcde ahen dhen 0000 i2c1stat 0204 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 0206 i2c1 address register 0000 i2c1msk 0208 i2c1 slave mode address mask register 0000 i2c1brg 020a baud rate generator register 0000 i2c1trn 020c i2c1 transmit register 00ff i2c1rcv 020e i2c1 receive register 0000 i2c2con1 0210 i2cen i2csidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c2con2 0212 pcie scie boen sdaht sbcde ahen dhen 0000 i2c2stat 0214 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c2add 0216 i2c2 address register 0000 i2c2msk 0218 i2c2 slave mode address mask register 0000 i2c2brg 021a baud rate generator register 0000 i2c2trn 021c i2c2 transmit register 00ff i2c2rcv 021e i2c2 receive register 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-14: uart1 and uart2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten usidl iren rtsmd uen1 uen0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 uart1 transmit register xxxx u1rxreg 0226 uart1 receive register 0000 u1brg 0228 baud rate generator prescaler register 0000 u2mode 0230 uarten usidl iren rtsmd uen1 uen0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u2txreg 0234 uart2 transmit register xxxx u2rxreg 0236 uart2 receive register 0000 u2brg 0238 baud rate generator prescaler register 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 53 dspic33epxxgs50x family table 4-15: spi1 and spi2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien spisidl spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi1con1 0242 dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd frmpol frmdly spiben 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 spi2stat 0260 spien spisidl spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi2con1 0262 dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi2con2 0264 frmen spifsd frmpol frmdly spiben 0000 spi2buf 0268 spi2 transmit and receive buffer register 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 54 ? 2013-2015 microchip technology inc. table 4-16: adc register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adcon1l 0300 adon a d s i d l 0000 adcon1h 0302 form shrres1 shrres0 0060 adcon2l 0304 refcie refercie e i e n shreisel2 shreisel1 shreisel0 shradcs6 shradcs5 shradcs4 shradcs3 shradcs2 shradcs1 shradcs0 0000 adcon2h 0306 refrdy referr shrsamc9 shrsamc8 shrsamc7 shrsamc6 shrsamc5 shrsamc4 shrsamc3 shrsamc2 shrsamc1 shrsamc 0 0000 adcon3l 0308 refsel2 refsel1 refsel0 suspend suspcie susprdy shrsamp cnvrtch swlctrg swctr g cnvchsel5 cnvchsel4 cnvchsel3 cnvchsel2 cnvchsel1 cnvchsel0 0000 adcon3h 030a clksel1 clksel0 clkdiv5 clkdiv4 clkdiv3 clkdiv2 clkdiv1 clkdiv0 shren c3en c2en c1en c0en 0000 adcon4l 030c synctrg3 synctrg2 synctrg1 synctrg0 samc3en samc2en samc1en samc0en 0000 adcon4h 030e c3chs1 c3chs0 c2chs1 c2chs0 c1chs1 c1chs0 c0chs1 c0chs0 0000 admod0l 0310 diff7 sign7 diff6 sign6 diff5 sign5 diff3 sign4 diff3 sign3 diff2 sign2 diff1 sign1 diff0 sign0 0000 admod0h 0312 diff15 ( 1 ) sign15 ( 1 ) diff14 ( 2 ) sign14 ( 2 ) diff13 ( 1 ) sign13 ( 1 ) diff12 ( 2 ) sign12 ( 2 ) diff11 ( 2 ) sign11 ( 2 ) diff10 ( 2 ) sign10 ( 2 ) diff9 ( 2 ) sign9 ( 2 ) diff8 ( 2 ) sign8 ( 2 ) 0000 admod1l 0314 diff21 sign21 diff20 sign20 diff19 sign19 diff18 sign18 diff17 ( 2 ) sign17 ( 2 ) diff16 ( 1 ) sign16 ( 1 ) 0000 adiel 0320 ie15 ( 1 ) ie14 ( 2 ) ie13 ( 1 ) ie12 ( 2 ) ie11 ( 2 ) ie10 ( 2 ) ie9 ( 2 ) ie8 ( 2 ) ie7 ie6 ie5 ie4 ie3 ie2 ie1 ie0 0000 adieh 0322 ie21 ie20 ie19 ie18 ie17 ( 2 ) ie16 ( 1 ) 0000 adstatl 0330 an15rdy ( 1 ) an14rdy ( 2 ) an13rdy ( 1 ) an12rdy ( 2 ) an11rdy ( 2 ) an10rdy ( 2 ) an9rdy ( 2 ) an8rdy ( 2 ) an7rdy an6rdy an5rdy an4rdy an3rdy an2rdy an1rdy an0rdy 0000 adstath 0332 an21rdy an20rdy an19rdy an18rdy an17rdy ( 2 ) an16rdy ( 1 ) 0000 adcmp0enl 0338 cmpen15 ( 1 ) cmpen14 ( 2 ) cmpen13 ( 1 ) cmpen12 ( 2 ) cmpen11 ( 2 ) cmpen10 ( 2 ) cmpen9 ( 2 ) cmpen8 ( 2 ) cmpen7 cmpen6 cmpen5 cmpen4 cmpen3 cmpen2 cmpen1 cmpen0 0000 adcmp0enh 033a cmpen21 cmpen20 cmpen19 cmpen18 cmpen17 ( 2 ) cmpen16 ( 1 ) 0000 adcmp0lo 033c adc comparator 0 low value register 0000 adcmp0hi 033e adc comparator 0 high value register 0000 adcmp1enl 0340 cmpen15 ( 1 ) cmpen14 ( 2 ) cmpen13 ( 1 ) cmpen12 ( 2 ) cmpen11 ( 2 ) cmpen10 ( 2 ) cmpen9 ( 2 ) cmpen8 ( 2 ) cmpen7 cmpen6 cmpen5 cmpen4 cmpen3 cmpen2 cmpen1 cmpen0 0000 adcmp1enh 0342 cmpen21 cmpen20 cmpen19 cmpen18 cmpen17 ( 2 ) cmpen16 ( 1 ) 0000 adcmp1lo 0344 adc comparator 1 low value register 0000 adcmp1hi 0346 adc comparator 1 high value register 0000 adfldat 0368 adc filter 0 results data register 0000 adfl1con 036a flen mode1 mode0 ovrsam2 ovrsam1 ovrsam0 ie rdy flchsel4 flchsel3 flchsel2 flchsel1 flchsel0 0000 adfl1dat 0368 adc filter 1 results data register 0000 adfl0con 036a flen mode1 mode0 ovrsam2 ovrsam1 ovrsam0 ie rdy flchsel4 flchsel3 flchsel2 flchsel1 flchsel0 0000 adtrig0l 0380 t r g s r c 1 < 4 : 0 > trgsrc0<4:0> 0000 adtrig0h 0382 t r g s r c 3 < 4 : 0 > trgsrc2<4:0> 0000 adtrig1l 0384 t r g s r c 5 < 4 : 0 > trgsrc4<4:0> 0000 adtrig1h 0386 t r g s r c 7 < 4 : 0 > trgsrc6<4:0> 0000 adtrig2l 0388 t r g s r c 9 < 4 : 0 > trgsrc8<4:0> 0000 adtrig2h 038a trgsrc11<4:0> trgsrc10<4:0> 0000 adtrig3l 038c trgsrc13<4:0> trgsrc12<4:0> 0000 adtrig3h 038e trgsrc15<4:0> trgsrc14<4:0> 0000 adtrig4l 0390 trgsrc17<4:0> trgsrc16<4:0> 0000 adtrig4h 0392 trgsrc19<4:0> trgsrc18<4:0> 0000 adtrig5l 0394 trgsrc21<4:0> trgsrc20<4:0> 0000 adcmp0con 03a0 chnl4 chnl3 chnl2 chnl1 chnl0 cmpen ie stat btwn hihi hilo lohi lolo 0000 adcmp1con 03a4 chnl4 chnl3 chnl2 chnl1 chnl0 cmpen ie stat btwn hihi hilo lohi lolo 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: implemented on dspic33epxxgs506 devices only. 2: implemented on dspic33epxxgs504/505 and dspic33epxxgs506 devices only. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 55 dspic33epxxgs50x family adlvltrgl 03d0 lvlen15 ( 1 ) lvlen14 lvlen13 ( 1 ) lvlen12 ( 2 ) lvlen11 ( 2 ) lvlen10 ( 2 ) lvlen9 ( 2 ) lvlen8 ( 2 ) lvlen7 lvlen6 lvlen5 lvlen4 lvlen3 lvlen2 lvlen1 lvlen0 0000 adlvltrgh 03d2 lvlen21 lvlen20 lvlen19 lvlen18 lvlen17 ( 2 ) lvlen16 ( 1 ) 0000 adcore0l 03d4 samc<9:0> 0000 adcore0h 03d6 eisel2 eisel1 eisel0 res1 res0 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 adcore1l 03d8 samc<9:0> 0000 adcore1h 03da eisel2 eisel1 eisel0 res1 res0 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 adcore2l 03dc samc<9:0> 0000 adcore2h 03de eisel2 eisel1 eisel0 res1 res0 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 adcore3l 03e0 samc<9:0> 0000 adcore3h 03e2 eisel2 eisel1 eisel0 res1 res0 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 adeiel 03f0 eien15 ( 1 ) eien14 ( 2 ) eien13 ( 1 ) eien12 ( 2 ) eien11 ( 2 ) eien10 ( 2 ) eien9 ( 2 ) eien8 ( 2 ) eien7 eien6 eien5 eien4 eien3 eien2 eien1 eien0 0000 adeieh 03f2 eien21 eien20 eien19 eien18 eien17 ( 2 ) eien16 ( 1 ) 0000 adeistatl 03f8 eistat15 ( 1 ) eistat14 ( 2 ) eistat13 ( 1 ) eistat12 ( 2 ) eistat11 ( 2 ) eistat10 ( 2 ) eistat9 ( 2 ) eistat8 ( 2 ) eistat7 eistat6 eistat5 eistat4 eistat3 eistat2 eistat1 eistat0 0000 adeistath 03fa eistat21 eistat20 eistat19 eistat18 eistat17 ( 2 ) eistat16 ( 1 ) 0000 adcon5l 0400 shrrdy c3rdy c2rdy c1rdy c0rdy shrpwr c3pwr c2pwr c1pwr c0pwr 0000 adcon5h 0402 warmtime3 warmtime2 warmtime1 warmtime0 shrcie c3cie c2cie c1cie c0cie 0000 adcal0l 0404 cal1rdy cal1skip cal1diff cal1en cal1run cal0rdy cal0skip cal0diff cal0en cal0run 0000 adcal0h 0406 cal3rdy cal3skip cal3diff cal3en cal3run cal2rdy cal2skip cal2diff cal2en cal2run 0000 adcal1h 040a cshrrdy cshrskip cshrdiff cshren cshrrun 0000 adcbuf0 040c adc data buffer 0 0000 adcbuf1 040e adc data buffer 1 0000 adcbuf2 0410 adc data buffer 2 0000 adcbuf3 0412 adc data buffer 3 0000 adcbuf4 0414 adc data buffer 4 0000 adcbuf5 0416 adc data buffer 5 0000 adcbuf6 041b adc data buffer 6 0000 adcbuf7 041a adc data buffer 7 0000 adcbuf8 041c adc data buffer 8 0000 adcbuf9 041e adc data buffer 9 0000 adcbuf10 0420 adc data buffer 10 0000 adcbuf11 0422 adc data buffer 11 0000 adcbuf12 0424 adc data buffer 12 0000 adcbuf13 0426 adc data buffer 13 0000 adcbuf14 0428 adc data buffer 14 0000 adcbuf15 042a adc data buffer 15 0000 adcbuf16 042c adc data buffer 16 0000 adcbuf17 042e adc data buffer 17 0000 adcbuf18 0430 adc data buffer 18 0000 adcbuf19 0432 adc data buffer 19 0000 adcbuf20 0434 adc data buffer 20 0000 adcbuf21 0436 adc data buffer 21 0000 table 4-16: adc register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: implemented on dspic33epxxgs506 devices only. 2: implemented on dspic33epxxgs504/505 and dspic33epxxgs506 devices only. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 56 ? 2013-2015 microchip technology inc. table 4-17: peripheral pin select output register map for dspic33epxxgs502 devices table 4-18: peripheral pin select output register map for dspic33epxxgs504/505 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0670 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 rp32r5rp32r4rp32r3rp32r2rp32r1rp32r0 0000 rpor1 0672 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 rp34r5rp34r4rp34r3rp34r2rp34r1rp34r0 0000 rpor2 0674 rp37r5 rp37r4 rp37r3 rp37r2 rp37r1 rp37r0 rp36r5rp36r4rp36r3rp36r2rp36r1rp36r0 0000 rpor3 0676 rp39r5 rp39r4 rp39r3 rp39r2 rp39r1 rp39r0 rp38r5rp38r4rp38r3rp38r2rp38r1rp38r0 0000 rpor4 0678 rp41r5 rp41r4 rp41r3 rp41r2 rp41r1 rp41r0 rp40r5rp40r4rp40r3rp40r2rp40r1rp40r0 0000 rpor5 067a rp43r5 rp43r4 rp43r3 rp43r2 rp43r1 rp43r0 rp42r5rp42r4rp42r3rp42r2rp42r1rp42r0 0000 rpor6 067c rp45r5 rp45r4 rp45r3 rp45r2 rp45r1 rp45r0 rp44r5rp44r4rp44r3rp44r2rp44r1rp44r0 0000 rpor7 067e rp47r5 rp47r4 rp47r3 rp47r2 rp47r1 rp47r0 rp46r5rp46r4rp46r3rp46r2rp46r1rp46r0 0000 rpor16 0690 rp177r5 rp177r4 rp177r3 rp177r2 rp177r1 rp177r0 rp176r5 rp176r4 rp176r3 rp176r2 rp176r1 rp176r0 0000 rpor17 0692 rp179r5 rp179r4 rp179r3 rp179r2 rp179r1 rp179r0 rp178r5 rp178r4 rp178r3 rp178r2 rp178r1 rp178r0 0000 rpor18 0694 rp181r5 rp181r4 rp181r3 rp181r2 rp181r1 rp181r0 rp180r5 rp180r4 rp180r3 rp180r2 rp180r1 rp180r0 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0670 rp33r5rp33r4rp33r3rp33r2rp33r1rp33r0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 0000 rpor1 0672 rp35r5rp35r4rp35r3rp35r2rp35r1rp35r0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 0000 rpor2 0674 rp37r5rp37r4rp37r3rp37r2rp37r1rp37r0 rp36r5rp36r4rp36r3rp36r2rp36r1rp36r0 0000 rpor3 0676 rp39r5 rp39r4 rp39r3 rp39r2 rp39r1 rp39r0 rp38r5 rp38r4 rp38r3 rp38r2 rp38r1 rp38r0 0000 rpor4 0678 rp41r5rp41r4rp41r3rp41r2rp41r1rp41r0 rp40r5rp40r4rp40r3rp40r2rp40r1rp40r0 0000 rpor5 067a rp43r5 rp43r4 rp43r3 rp43r2 rp43r1 rp43r0 rp42r5 rp42r4 rp42r3 rp42r2 rp42r1 rp42r0 0000 rpor6 067c rp45r5 rp45r4 rp45r3 rp45r2 rp45r1 rp45r0 rp44r5 rp44r4 rp44r3 rp44r2 rp44r1 rp44r0 0000 rpor7 067e rp47r5 rp47r4 rp47r3 rp47r2 rp47r1 rp47r0 rp46r5 rp46r4 rp46r3 rp46r2 rp46r1 rp46r0 0000 rpor8 0680 rp49r5 rp49r4 rp49r3 rp49r2 rp49r1 rp49r0 rp48r5 rp48r4 rp48r3 rp48r2 rp48r1 rp48r0 0000 rpor9 0682 rp51r5 rp51r4 rp51r3 rp51r2 rp51r1 rp51r0 rp50r5 rp50r4 rp50r3 rp50r2 rp50r1 rp50r0 0000 rpor10 0684 rp53r5 rp53r4 rp53r3 rp53r2 rp53r1 rp53r0 rp52r5 rp52r4 rp52r3 rp52r2 rp52r1 rp52r0 0000 rpor11 0686 rp55r5 rp55r4 rp55r3 rp55r2 rp55r1 rp55r0 rp54r5 rp54r4 rp54r3 rp54r2 rp54r1 rp54r0 0000 rpor12 0688 rp57r5 rp57r4 rp57r3 rp57r2 rp57r1 rp57r0 rp56r5 rp56r4 rp56r3 rp56r2 rp56r1 rp56r0 0000 rpor13 068a rp59r5 rp59r4 rp59r3 rp59r2 rp59r1 rp59r0 rp58r5 rp58r4 rp58r3 rp58r2 rp58r1 rp58r0 0000 rpor14 068c rp61r5 rp61r4 rp61r3 rp61r2 rp61r1 rp61r0 rp60r5 rp60r4 rp60r3 rp60r2 rp60r1 rp60r0 0000 rpor16 0690 rp177r5 rp177r4 rp177r3 rp177r2 rp177r1 rp177r0 rp176r5 rp176r4 rp176r3 rp176r2 rp176r1 rp176r0 0000 rpor17 0692 rp179r5 rp179r4 rp179r3 rp179r2 rp179r1 rp179r0 rp178r5 rp178r4 rp178r3 rp178r2 rp178r1 rp178r0 0000 rpor18 0694 rp181r5 rp181r4 rp181r3 rp181r2 rp181r1 rp181r0 rp180r5 rp180r4 rp180r3 rp180r2 rp180r1 rp180r0 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 57 dspic33epxxgs50x family table 4-19: peripheral pin select output register map for dspic33epxxgs506 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0670 rp33r5rp33r4rp33r3rp33r2rp33r1rp33r0 rp32r5rp32r4rp32r3rp32r2rp32r1rp32r0 0000 rpor1 0672 rp35r5rp35r4rp35r3rp35r2rp35r1rp35r0 rp34r5rp34r4rp34r3rp34r2rp34r1rp34r0 0000 rpor2 0674 rp37r5rp37r4rp37r3rp37r2rp37r1rp37r0 rp36r5rp36r4rp36r3rp36r2rp36r1rp36r0 0000 rpor3 0676 rp39r5 rp39r4 rp39r3 rp39r2 rp39r1 rp39r0 rp38r5rp38r4rp38r3rp38r2rp38r1rp38r0 0000 rpor4 0678 rp41r5rp41r4rp41r3rp41r2rp41r1rp41r0 rp40r5rp40r4rp40r3rp40r2rp40r1rp40r0 0000 rpor5 067a rp43r5 rp43r4 rp43r3 rp43r2 rp43r1 rp43r0 rp42r5rp42r4rp42r3rp42r2rp42r1rp42r0 0000 rpor6 067c rp45r5 rp45r4 rp45r3 rp45r2 rp45r1 rp45r0 rp44r5rp44r4rp44r3rp44r2rp44r1rp44r0 0000 rpor7 067e rp47r5 rp47r4 rp47r3 rp47r2 rp47r1 rp47r0 rp46r5rp46r4rp46r3rp46r2rp46r1rp46r0 0000 rpor8 0680 rp49r5 rp49r4 rp49r3 rp49r2 rp49r1 rp49r0 rp48r5rp48r4rp48r3rp48r2rp48r1rp48r0 0000 rpor9 0682 rp51r5 rp51r4 rp51r3 rp51r2 rp51r1 rp51r0 rp50r5rp50r4rp50r3rp50r2rp50r1rp50r0 0000 rpor10 0684 rp53r5 rp53r4 rp53r3 rp53r2 rp53r1 rp53r0 rp52r5rp52r4rp52r3rp52r2rp52r1rp52r0 0000 rpor11 0686 rp55r5 rp55r4 rp55r3 rp55r2 rp55r1 rp55r0 rp54r5rp54r4rp54r3rp54r2rp54r1rp54r0 0000 rpor12 0688 rp57r5 rp57r4 rp57r3 rp57r2 rp57r1 rp57r0 rp56r5rp56r4rp56r3rp56r2rp56r1rp56r0 0000 rpor13 068a rp59r5 rp59r4 rp59r3 rp59r2 rp59r1 rp59r0 rp58r5rp58r4rp58r3rp58r2rp58r1rp58r0 0000 rpor14 068c rp61r5 rp61r4 rp61r3 rp61r2 rp61r1 rp61r0 rp60r5rp60r4rp60r3rp60r2rp60r1rp60r0 0000 rpor15 068e rp63r5 rp63r4 rp63r3 rp63r2 rp63r1 rp63r0 rp62r5rp62r4rp62r3rp62r2rp62r1rp62r0 0000 rpor16 0690 rp177r5 rp177r4 rp177r3 rp177r2 rp177r1 rp177r0 rp176r5 rp176r4 rp176r3 rp176r2 rp176r1 rp176r0 0000 rpor17 0692 rp179r5 rp179r4 rp179r3 rp179r2 rp179r1 rp179r0 rp178r5 rp178r4 rp178r3 rp178r2 rp178r1 rp178r0 0000 rpor18 0694 rp181r5 rp181r4 rp181r3 rp181r2 rp181r1 rp181r0 rp180r5 rp180r4 rp180r3 rp180r2 rp180r1 rp180r0 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 58 ? 2013-2015 microchip technology inc. table 4-20: peripheral pin select input register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 06a0 int1r<7:0> 0000 rpinr1 06a2 i n t 2 r < 7 : 0 > 0000 rpinr2 06a4 t1ckr<7:0> 0000 rpinr3 06a6 t3ckr7 t3ckr6 t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3c kr0 t2ckr7 t2ckr6 t2ckr5 t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 0000 rpinr7 06ae ic2r7 ic2r6 ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic 2r0 ic1r7 ic1r6 ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 0000 rpinr8 06b0 ic4r7 ic4r6 ic4r5 ic4r4 ic4r3 ic4r2 ic4r1 ic 4r0 ic3r7 ic3r6 ic3r5 ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 0000 rpinr11 06b6 o c f a r < 7 : 0 > 0000 rpinr12 06b8 flt2r7 flt2r6 flt2r5 flt2r4 flt2r3 flt2r2 flt2r1 f lt2r0 flt1r7 flt1r6 flt1r5 flt1r4 flt1r3 flt1r2 flt1r1 flt1r0 0000 rpinr13 06ba flt4r7 flt4r6 flt4r5 flt4r4 flt4r3 flt4r2 flt4r1 f lt4r0 flt3r7 flt3r6 flt3r5 flt3r4 flt3r3 flt3r2 flt3r1 flt3r0 0000 rpinr18 06c4 u1ctsr7 u1ctsr6 u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1cts r1 u1cts0 u1rxr7 u1rxr6 u1rxr5 u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 0000 rpinr19 06c6 u2ctsr7 u2ctsr6 u2ctsr5 u2ctsr4 u2ctsr3 u2ctsr2 u2cts r1 u2ctsr0 u2rxr7 u2rxr6 u2rxr5 u2rxr4 u2rxr3 u2rxr2 u2rxr1 u2rxr0 0000 rpinr20 06c8 sck1inr7 sck1inr6 sck1inr5 sck1inr4 sck1inr3 sck1inr2 sck 1inr1 sck1inr0 sdi1r7 sdi1r6 sdi1r5 sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 0000 rpinr21 06ca ss1r<7:0> 0000 rpinr22 06cc sck2inr7 sck2inr6 sck2inr5 sck2inr4 sck2inr3 sck2inr2 sck2 inr1 sck2inr0 sdi2r7 sdi2r6 sdi2r5 sdi2r4 sdi2r3 sdi2r2 sdi2r1 sdi2r0 0000 rpinr23 06ce ss2r<7:0> 0000 rpinr37 06ea synci1r<7:0> 0000 rpinr38 06ec s y n c i 2 r < 7 : 0 > 0000 rpinr42 06f4 flt6r7 flt6r6 flt6r5 flt6r4 flt6r3 flt6r2 flt6r1 f lt6r0 flt5r7 flt5r6 flt5r5 flt5r4 flt5r3 flt5r2 flt5r1 flt5r0 0000 rpinr43 06f6 flt8r7 flt8r6 flt8r5 flt8r4 flt8r3 flt8r2 flt8r1 f lt8r0 flt7r7 flt7r6 flt7r5 flt7r4 flt7r3 flt7r2 flt7r1 flt7r0 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 59 dspic33epxxgs50x family table 4-21: nvm register map table 4-22: system control register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0728 wr wren wrerr nvmsidl sftswp p2activ rpdf urerr nvmop3 nvmop2 nvmop1 nvmop0 0000 nvmadr 072a nvmadr<15:0> 0000 nvmadru 072c nvmadr<23:16> 0000 nvmkey 072e nvmkey<7:0> 0000 nvmsrcadr 0730 nvm source data address register, lower word (nvmsrcadr<15:0>) 0000 nvmsrcadrh 0732 nvm source data address register, upper byte (nvmsrcadr<23:16> 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr vregsf cm vregs extr swr swdten wdto sleep idle bor por note 1 osccon 0742 cosc2 cosc1 cosc0 nosc2 nosc1 nosc0 clklock iolock lock c f o s w e n note 2 clkdiv 0744 roi doze2 doze1 doze0 dozen frcdiv2 frcdiv1 frcdiv0 pllpost1 pllpost0 pllpre4 pllpre3 pllpre2 pllpre1 pllpre0 3040 pllfbd 0746 p l l d i v < 8 : 0 > 0030 osctun 0748 tun<5:0> 0000 lfsr 074c lfsr<14:0> 0000 refocon 074e roon rosslp rosel rodiv3 rodiv2 rodiv1 rodiv0 0000 aclkcon 0750 enapll apllck selaclk apstsclr2 apstsclr1 apstsclr0 asrcsel frcsel 2740 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: rcon register reset values are dependent on the type of reset. 2: osccon register reset values are dependent on the configuration fuses. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 60 ? 2013-2015 microchip technology inc. table 4-23: pmd register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md p w m m d i2c1md u2md u1md spi2md spi1md adcmd 0000 pmd2 0762 ic4md ic3md ic2md ic1md oc4md oc3md oc2md oc1md 0000 pmd3 0764 c m p m d i2c2md 0000 pmd4 0766 refomd 0000 pmd6 076a pwm5md pwm4md pwm3md pwm2md pwm1md 0000 pmd7 076c cmp4md cmp3md cmp2md cmp1md pga1md 0000 pmd8 076e p g a 2 m da b g m d ccsmd 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-24: constant-current source register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets isrccon 0500 isrcen outsel2 outsel1 outsel0 isrccal5 isrccal4 isrccal3 isrccal2 isrccal1 isrccal0 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-25: programmable gain amplifier register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pga1con 0504 pgaen pgaoen selpi2 selpi1 selpi0 selni2 selni1 selni0 gain2 gain1 gain0 0000 pga1cal 0506 pgacal<5:0> 0000 pga2con 0508 pgaen pgaoen selpi2 selpi1 selpi0 selni2 selni1 selni0 gain2 gain1 gain0 0000 pga2cal 050a pgacal<5:0> 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 61 dspic33epxxgs50x family table 4-26: analog comparator register map table 4-27: jtag interface register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets cmp1con 0540 cmpon cmpsidl hyssel1 hyssel0 fltren fclksel dacoe insel1 insel0 extref hyspol cmpstat altinp cmppol range 0000 cmp1dac 0542 c m r e f < 1 1 : 0 > 0000 cmp2con 0544 cmpon cmpsidl hyssel1 hyssel0 fltren fclksel dacoe insel1 insel0 extref hyspol cmpstat altinp cmppol range 0000 cmp2dac 0546 c m r e f < 1 1 : 0 > 0000 cmp3con 0548 cmpon cmpsidl hyssel1 hyssel0 fltren fclksel dacoe insel1 insel0 extref hyspol cmpstat altinp cmppol range 0000 cmp3dac 054a c m r e f < 1 1 : 0 > 0000 cmp4con 054c cmpon cmpsidl hyssel1 hyssel0 fltren fclksel dacoe insel1 insel0 extref hyspol cmpstat altinp cmppol range 0000 cmp4dac 054e c m r e f < 1 1 : 0 > 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets jdatah 0ff0 jdatah<11:0> xxxx jdatal 0ff2 jdatal<15:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 62 ? 2013-2015 microchip technology inc. table 4-28: porta register map for dspic33epxxgs502 devices table 4-29: portb register map for dspic33epxxgs502 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 0e00 trisa<4:0> 001f porta 0e02 r a < 4 : 0 > 0000 lata 0e04 l a t a < 4 : 0 > 0000 odca 0e06 odca<4:0> 0000 cnena 0e08 cniea<4:0> 0000 cnpua 0e0a cnpua<4:0> 0000 cnpda 0e0c cnpda<4:0> 0000 ansela 0e0e a n s a < 2 : 0 > 0007 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 0e10 trisb<15:0> ffff portb 0e12 rb<15:0> xxxx latb 0e14 latb<15:0> xxxx odcb 0e16 odcb<15:0> 0000 cnenb 0e18 cnieb<15:0> 0000 cnpub 0e1a cnpub<15:0> 0000 cnpdb 0e1c cnpdb<15:0> 0000 anselb 0e1e ansb<10:9> ansb<7:0> 06ff legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 63 dspic33epxxgs50x family table 4-30: porta register map for dspic33epxxgs504/505 devices table 4-31: portb register map for dspic33epxxgs504/505 devices table 4-32: portc register map for dspic33epxxgs504/505 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 0e00 trisa<4:0> 001f porta 0e02 r a < 4 : 0 > 0000 lata 0e04 l a t a < 4 : 0 > 0000 odca 0e06 odca<4:0> 0000 cnena 0e08 cniea<4:0> 0000 cnpua 0e0a cnpua<4:0> 0000 cnpda 0e0c cnpda<4:0> 0000 ansela 0e0e a n s a < 2 : 0 > 0007 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 0e10 trisb<15:0> ffff portb 0e12 rb<15:0> xxxx latb 0e14 latb<15:0> xxxx odcb 0e16 odcb<15:0> 0000 cnenb 0e18 cnieb<15:0> 0000 cnpub 0e1a cnpub<15:0> 0000 cnpdb 0e1c cnpdb<15:0> 0000 anselb 0e1e a n s b < 1 0 : 9 > ansb<7:5> ansb<3:0> 06ef legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 0e20 trisc<13:0> 3fff portc 0e22 rc<13:0> xxxx latc 0e24 latc<13:0> xxxx odcc 0e26 odcc<13:0> 0000 cnenc 0e28 cniec<13:0> 0000 cnpuc 0e2a cnpuc<13:0> 0000 cnpdc 0e2c cnpdc<13:0> 0000 anselc 0e2e ansc<12:9> ansc<6:4> ansc<2:0> 1e77 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 64 ? 2013-2015 microchip technology inc. table 4-33: porta register map for dspic33epxxgs506 devices table 4-34: portb register map for dspic33epxxgs506 devices table 4-35: portc register map for dspic33epxxgs506 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bi t 0 all resets trisa 0e00 trisa<4:0> 001f porta 0e02 r a < 4 : 0 > 0000 lata 0e04 l a t a < 4 : 0 > 0000 odca 0e06 odca<4:0> 0000 cnena 0e08 cniea<4:0> 0000 cnpua 0e0a cnpua<4:0> 0000 cnpda 0e0c cnpda<4:0> 0000 ansela 0e0e a n s a < 2 : 0 > 0007 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 0e10 trisb<15:0> ffff portb 0e12 rb<15:0> xxxx latb 0e14 latb<15:0> xxxx odcb 0e16 odcb<15:0> 0000 cnenb 0e18 cnieb<15:0> 0000 cnpub 0e1a cnpub<15:0> 0000 cnpdb 0e1c cnpdb<15:0> 0000 anselb 0e1e ansb<10:9> ansb<7:5> ansb<3:0> 06ef legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 0e20 trisc<15:0> ffff portc 0e22 rc<15:0> xxxx latc 0e24 latc<15:0> xxxx odcc 0e26 odcc<15:0> 0000 cnenc 0e28 cniec<15:0> 0000 cnpuc 0e2a cnpuc<15:0> 0000 cnpdc 0e2c cnpdc<15:0> 0000 anselc 0e2e ansc<12:9> ansc<6:4> ansc<2:0> 1e77 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 65 dspic33epxxgs50x family table 4-36: portd register map for dspic33epxxgs506 devices sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisd 0e30 trisd<15:0> ffff portd 0e32 rd<15:0> xxxx latd 0e34 latd<15:0> xxxx odcd 0e36 odcd<15:0> 0000 cnend 0e38 cnied<15:0> 0000 cnpud 0e3a cnpud<15:0> 0000 cnpdd 0e3c cnpdd<15:0> 0000 anseld 0e3e ansd13 ansd7 ansd2 6084 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 66 ? 2013-2015 microchip technology inc. 4.5.1 paged memory scheme the dspic33epxxgs50x architecture extends the available data space through a paging scheme, which allows the available data space to be accessed using mov instructions in a linear fashion for pre- and post-modified effective addresses (eas). the upper half of the base data space address is used in conjunction with the data space page (dsrpag) register to form the program space visibility (psv) address. the data space page (dsrpag) register is located in the sfr space. construction of the psv address is shown in figure 4-9 . when dsrpag<9> = 1 and the base address bit, ea<15> = 1 , the dsrpag<8:0> bits are concatenated onto ea<14:0> to form the 24-bit psv read address. the paged memory scheme provides access to multiple 32-kbyte windows in the psv memory. the data space page (dsrpag) register, in combination with the upper half of the data space address, can provide up to 8 mbytes of psv address space. the paged data memory space is shown in figure 4-10 . the program space (ps) can be accessed with a dsrpag of 0x200 or greater. only reads from ps are supported using the dsrpag. figure 4-9: program space visibi lity (psv) read address generation 1 dsrpag<8:0> 9 bits ea 15 bits select byte 24-bit psv ea select ea (dsrpag = dont care) no eds access select 16-bit ds ea byte ea<15> = 0 dsrpag 1 ea<15> note: ds read access when dsrpag = 0x000 will force an address error trap. = 1 dsrpag<9> generate psv address 0 downloaded from: http:///
? 2013-2015 microchip tec hnology inc. ds70005127c-page 67 dspic33epxxgs50x family figure 4-10: paged data memory space program memory 0x0000 sfr registers 0x0fff 0x1000 up to 8-kbyte 0x2fff local data space 32-kbyte psv window 0xffff 0x3000 program space 0x00_0000 0x7f_ffff (lsw C <15:0>) 0x0000 (dsrpag = 0x200) psv program memory (dsrpag = 0x2ff) (dsrpag = 0x300) (dsrpag = 0x3ff) 0x7fff 0x0000 0x7fff 0x0000 0x7fff 0x0000 0x7fff ds_addr<14:0> ds_addr<15:0> (lsw) psv program memory (msb) table address space (tblpag<7:0>) program memory 0x00_0000 0x7f_ffff (msb C <23:16>) 0x0000 (tblpag = 0x00) 0xffff ds_addr<15:0> lsw using tblrdl / tblwtl , msb using tblrdh / tblwth 0x0000 (tblpag = 0x7f) 0xffff lsw using tblrdl / tblwtl , msb using tblrdh / tblwth (instruction & data) no writes allowed no writes allowed no writes allowed no writes allowed ram 0x7fff 0x8000 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 68 ? 2013-2015 microchip technology inc. when a psv page overflow or underflow occurs, ea<15> is cleared as a result of the register indirect ea calculation. an overflow or underflow of the ea in the psv pages can occur at the page boundaries when: the initial address, prior to modification, addresses the psv page the ea calculation uses pre- or post-modified register indirect addressing; however, this does not include register offset addressing in general, when an overflow is detected, the dsrpag register is incremented and the ea<15> bit is set to keep the base address within the psv window. when an underflow is detected, the dsrpag register is decremented and the ea<15> bit is set to keep the base address within the psv window. this creates a linear psv address space, but only when using register indirect addressing modes. exceptions to the operation described above arise when entering and exiting the boundaries of page 0 and psv spaces. tab l e 4 - 37 lists the effects of overflow and underflow scenarios at different boundaries. in the following cases, when overflow or underflow occurs, the ea<15> bit is set and the dsrpag is not modified; therefore, the ea will wrap to the beginning of the current page: register indirect with register offset addressing modulo addressing bit-reversed addressing table 4-37: overflow and underflow scenarios at page 0 and psv space boundaries ( 2 , 3 , 4 ) o/u, r/w operation before after dsxpag ds ea<15> page description dsxpag ds ea<15> page description o, read [++wn] or [wn++] dsrpag = 0x2ff 1 psv: last lsw page dsrpag = 0x300 1 psv: first msb page o, read dsrpag = 0x3ff 1 psv: last msb page dsrpag = 0x3ff 0 see note 1 u, read [--wn] or [wn--] dsrpag = 0x001 1 psv page dsrpag = 0x001 0 see note 1 u, read dsrpag = 0x200 1 psv: first lsw page dsrpag = 0x200 0 see note 1 u, read dsrpag = 0x300 1 psv: first msb page dsrpag = 0x2ff 1 psv: last lsw page legend: o = overflow, u = underflow, r = read, w = write note 1: the register indirect addressing now addresses a location in the base data space (0x0000-0x7fff). 2: an eds access, with dsrpag = 0x000, will generate an address error trap. 3: only reads from ps are supported using dsrpag. 4: pseudolinear addressing is not supported for large offsets. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 69 dspic33epxxgs50x family 4.5.2 extended x data space the lower portion of the base address space range, between 0x0000 and 0x7fff, is always accessible, regardless of the contents of the data space page reg- ister. it is indirectly addressable through the register indirect instructions. it can be regarded as being located in the default eds page 0 (i.e., eds address range of 0x000000 to 0x007fff with the base address bit, ea<15> = 0 , for this address range). however, page 0 cannot be accessed through the upper 32 kbytes, 0x8000 to 0xffff, of base data space in combination with dsrpag = 0x00. consequently, dsrpag is initialized to 0x001 at reset. the remaining psv pages are only accessible using the dsrpag register in combination with the upper 32 kbytes, 0x8000 to 0xffff, of the base address, where base address bit, ea<15> = 1 . 4.5.3 software stack the w15 register serves as a dedicated software stack pointer (ssp), and is automatically modified by exception processing, subroutine calls and returns; however, w15 can be referenced by any instruction in the same manner as all other w registers. this simpli- fies reading, writing and manipulating the stack pointer (for example, creating stack frames). w15 is initialized to 0x1000 during all resets. this address ensures that the ssp points to valid ram in all dspic33epxxgs50x devices and permits stack avail- ability for non-maskable trap exceptions. these can occur before the ssp is initialized by the user software. you can reprogram the ssp during initialization to any location within data space. the software stack pointer always points to the first available free word and fills the software stack, working from lower toward higher addresses. figure 4-11 illustrates how it pre-decrements for a stack pop (read) and post-increments for a stack push (writes). when the pc is pushed onto the stack, pc<15:0> are pushed onto the first available stack word, then pc<22:16> are pushed into the second available stack location. for a pc push during any call instruction, the msb of the pc is zero-extended before the push, as shown in figure 4-11 . during exception processing, the msb of the pc is concatenated with the lower 8 bits of the cpu status register, sr. this allows the contents of srl to be preserved automatically during interrupt processing. figure 4-11: call stack frame note 1: dsrpag should not be used to access page 0. an eds access with dsrpag set to 0x000 will generate an address error trap. 2: clearing the dsrpag in software has no effect. note: to protect against misaligned stack accesses, w15<0> is fixed to 0 by the hardware. note 1: to maintain system stack pointer (w15) coherency, w15 is never subject to (eds) paging, and is therefore, restricted to an address range of 0x0000 to 0xffff. the same applies to the w14 when used as a stack frame pointer (sfa = 1 ). 2: as the stack can be placed in, and can access x and y spaces, care must be taken regarding its use, particularly with regard to local automatic variables in a c development environment pc<15:1> b000000000 0 15 w15 (before call ) w15 (after call ) stack grows toward higher address 0x0000 pc<22:16> call subr downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 70 ? 2013-2015 microchip technology inc. 4.6 instruction addressing modes the addressing modes shown in ta b l e 4 - 3 8 form the basis of the addressing modes optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instructions differ from those in the other instruction types. 4.6.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.6.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 operand 2 where operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as wb. operand 2 can be a w register fetched from data memory or a 5-bit literal. the result location can either be a w register or a data memory location. the following addressing modes are supported by mcu instructions: register direct register indirect register indirect post-modified register indirect pre-modified 5-bit or 10-bit literal table 4-38: fundamental addressing modes supported note: not all instructions support all the addressing modes given above. individ- ual instructions can support different subsets of these addressing modes. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn form the effective address (ea). register indirect post-modified the contents of wn form the ea. wn i s post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 71 dspic33epxxgs50x family 4.6.3 move and accumulator instructions move instructions, and the dsp accumulator class of instructions, provide a greater degree of address- ing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accumulator instructions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: register direct register indirect register indirect post-modified register indirect pre-modified register indirect with register offset (indexed) register indirect with literal offset 8-bit literal 16-bit literal 4.6.4 mac instructions the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand prefetch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must therefore, be valid addresses within x data space for w8 and w9, and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: register indirect register indirect post-modified by 2 register indirect post-modified by 4 register indirect post-modified by 6 register indirect with register offset (indexed) 4.6.5 other instructions besides the addressing modes outlined previously, some instructions use literal constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as ulnk , the source of an operand or result is implied by the opcode itself. certain operations, such as a nop , do not have any operands. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. how- ever, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 72 ? 2013-2015 microchip technology inc. 4.7 modulo addressing modulo addressing mode is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circular buffer can be supported in each of the x (which also provides the point- ers into program space) and y data spaces. modulo addressing can operate on any w register pointer. how- ever, it is not advisable to use w14 or w15 for modulo addressing since these two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be config- ured to operate in only one direction, as there are certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing buffers), based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.7.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see tab l e 4 - 2 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.7.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags, as well as a w register field to specify the w address registers. the xwm and ywm fields select the registers that operate with modulo addressing: if xwm = 1111 , x ragu and x wagu modulo addressing is disabled if ywm = 1111 , y agu modulo addressing is disabled the x address space pointer w (xwm) register, to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 4-2 ). modulo addressing is enabled for x data space when xwm is set to any value other than 1111 and the xmoden bit is set (modcon<15>). the y address space pointer w (ywm) register, to which modulo addressing is to be applied, is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than 1111 and the ymoden bit (modcon<14>) is set. figure 4-12: modulo address ing operation example note: y space modulo addressing ea calcula- tions assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 73 dspic33epxxgs50x family 4.7.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: the upper boundary addresses for incrementing buffers the lower boundary addresses for decrementing buffers it is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, therefore, jump beyond boundaries and still be adjusted correctly. 4.8 bit-reversed addressing bit-reversed addressing mode is intended to simplify data reordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.8.1 bit-reversed addressing implementation bit-reversed addressing mode is enabled when all of these situations are met: bwmx bits (w register selection) in the modcon register are any value other than 1111 (the stack cannot be accessed using bit-reversed addressing) the bren bit is set in the xbrev register the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last n bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed addressing modifier, or pivot point, which is typically a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indirect with pre-increment or post- increment addressing and word-sized data writes. it does not function for any other addressing mode or for byte-sized data and normal addresses are generated instead. when bit-reversed addressing is active, the w address pointer is always added to the address modifier (xb) and the offset associated with the register indirect addressing mode is ignored. in addi- tion, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre-modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo addressing correction is performed, but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing can be enabled simultaneously using the same w register, but bit- reversed addressing operation will always take precedence for data writes when enabled. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 74 ? 2013-2015 microchip technology inc. figure 4-13: bit-reversed addressing example table 4-39: bit-reversed addres sing sequence (16-entry) normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 75 dspic33epxxgs50x family 4.9 interfacing program and data memory spaces the dspic33epxxgs50x family architecture uses a 24-bit wide program space (ps) and a 16-bit wide data space (ds). the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data suc- cessfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the architecture of the dspic33epxxgs50x family devices provides two methods by which program space can be accessed during operation: using table instructions to access individual bytes or words anywhere in the program space remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. the application can only access the least significant word of the program word. table 4-40: program space address construction figure 4-14: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xxx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 program counter 23 bits program counter (1) tblpag 8 bits ea 16 bits byte select 0 1/0 user/configuration table operations (2) space select 24 bits 1/0 note 1: the least significant bit (lsb) of program space addresses is always fixed as 0 to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. table read operations are permitted in the configuration memory space. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 76 ? 2013-2015 microchip technology inc. 4.9.1 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>) - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is 1 ; the lower byte is selected when it is 0 . tblrdh (table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. the phantom byte (d<15:8>) is always 0 . - in byte mode, this instruction maps the upper or lower byte of the program word to d<7:0> of the data address in the tblrdl instruc- tion. the data is always 0 when the upper phantom byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 flash program memory . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user application and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-15: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 phantom byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x0000000x800000 0x0200000x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; wr ite operations are also valid in the user memory area. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 77 dspic33epxxgs50x family 5.0 flash program memory the dspic33epxxgs50x family devices contain internal flash program memory for storing and executing application code. the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in three ways: in-circuit serial programming? (icsp?) programming capability enhanced in-circuit serial programming (enhanced icsp) run-time self-programming (rtsp) icsp allows for a dspic33epxxgs50x family device to be serially programmed while in the end application circuit. this is done with a programming clock and pro- gramming data (pgecx/pgedx) line, and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. enhanced in-circuit serial programming uses an on-board bootloader, known as the program executive, to manage the programming process. using an spi data frame format, the program executive can erase, program and verify program memory. for more informa- tion on enhanced icsp, see the device programming specification. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data with a single program memory word and erase program mem- ory in blocks or pages of 512 instructions (1536 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w register, specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to flash programming (ds70609) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ) 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 78 ? 2013-2015 microchip technology inc. 5.2 rtsp operation the dspic33epxxgs50x family flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a single page (8 rows or 512 instructions) of memory at a time and to program one row at a time. it is possible to program two instructions at a time as well. the page erase and single row write blocks are edge- aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respec- tively. figure 26-14 in section 26.0 electrical characteristics lists the typical erase and programming times. row programming is performed by loading 192 bytes into data memory and then loading the address of the first byte in that row into the nvmsrcadr register. once the write has been initiated, the device will automatically load the write latches and increment the nvmsrcadr and the nvmadr(u) registers until all bytes have been programmed. the rpdf bit (nvmcon<9>) selects the format of the stored data in ram to be either compressed or uncompressed. see figure 5-2 for data formatting. compressed data helps to reduce the amount of required ram by using the upper byte of the second word for the msb of the second instruction. the basic sequence for rtsp word programming is to use the tblwtl and tblwth instructions to load two of the 24-bit instructions into the write latches found in configuration memory space. refer to figure 4-1 through figure 4-4 for write latch addresses. program- ming is performed by unlocking and setting the control bits in the nvmcon register. all erase and program operations may optionally use the nvm interrupt to signal the successful completion of the operation. for example, when performing flash write operations on the inactive partition in dual partition mode, where the cpu remains running, it is necessary to wait for the nvm interrupt before programming the next block of flash program memory. figure 5-2: uncompressed/ compressed format 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the program- ming operation is finished. setting the wr bit (nvmcon<15>) starts the operation and the wr bit is automatically cleared when the operation is finished. 5.3.1 programming algorithm for flash program memory programmers can program two adjacent words (24 bits x 2) of program flash memory at a time on every other word address boundary (0x000000, 0x000004, 0x000008, etc.). to do this, it is necessary to erase the page that contains the desired address of the location the user wants to change. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user application must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s. msb1 0x00 lsw2 lsw1 increasing address 0 7 15 even byte address msb2 0x00 msb1 msb2 lsw2 lsw1 increasing address 0 7 15 even byte address uncompressed format (rpdf = 0 ) compressed format (rpdf = 1 ) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 79 dspic33epxxgs50x family 5.4 dual partition flash configuration for dspic33ep64gs50x devices operating in dual partition flash program memory modes, the inactive partition can be erased and programmed without stall- ing the processor. the same programming algorithms are used for programming and erasing the flash in the inactive partition, as described in section 5.2 rtsp operation . on top of the page erase option, the entire flash memory of the inactive partition can be erased by configuring the nvmop<3:0> bits in the nvmcon register. 5.4.1 flash partition swapping the boot sequence number is used for determining the active partition at start-up and is encoded within the fbtseq configuration register bits. unlike most configuration registers, which only utilize the lower 16 bits of the program memory, fbtseq is a 24-bit configuration word. the boot sequence number (bseq) is a 12-bit value and is stored in fbtseq twice. the true value is stored in bits, fbtseq<11:0>, and its complement is stored in bits, fbtseq<23:12>. at device reset, the sequence numbers are read and the partition with the lowest sequence number becomes the active partition. if one of the boot sequence numbers is invalid, the device will select the partition with the valid boot sequence number, or default to partition 1 if both sequence numbers are invalid. see section 23.0 special features for more information. the bootswp instruction provides an alternative means of swapping the active and inactive partitions (soft swap) without the need for a device reset. the bootswp must always be followed by a goto instruc- tion. the bootswp instruction swaps the active and inactive partitions, and the pc vectors to the location specified by the goto instruction in the newly active partition. it is important to note that interrupts should temporarily be disabled while performing the soft swap sequence and that after the partition swap, all peripherals and interrupts which were enabled remain enabled. addi- tionally, the ram and stack will maintain state after the switch. as a result, it is recommended that applications using soft swaps jump to a routine that will reinitialize the device in order to ensure the firmware runs as expected. the configuration registers will have no effect during a soft swap. for robustness of operation, in order to execute the bootswp instruction, it is necessary to execute the nvm unlocking sequence as follows: 1. write 0x55 to nvmkey. 2. write 0xaa to nvmkey. 3. execute the bootswp instruction. if the unlocking sequence is not performed, the bootswp instruction will be executed as a forced nop and a goto instruction, following the bootswp instruc- tion, will be executed, causing the pc to jump to that location in the current operating partition. the sftswp and p2activ bits in the nvmcon register are used to determine a successful swap of the active and inactive partitions, as well as which partition is active. after the bootswp and goto instructions, the sftswp bit should be polled to verify the partition swap has occurred and then cleared for the next panel swap event. 5.4.2 dual partition modes while operating in dual partition mode, dspic33ep64gs50x family devices have the option for both partitions to have their own defined security seg- ments, as shown in figure 23-4 . alternatively, the device can operate in protected dual partition mode, where partition 1 becomes permanently erase/write-protected. protected dual partition mode allows for a factory default mode, which provides a fail-safe backup image to be stored in partition 1. dspic33ep64gs50x family devices can also operate in privileged dual partition mode, where additional security protections are implemented to allow for pro- tection of intellectual property when multiple parties have software within the device. in privileged dual par- tition mode, both partitions place additional restrictions on the bslim register. these prevent changes to the size of the boot segment and general segment, ensuring that neither segment will be altered. 5.5 flash memory resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 5.5.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools note 1: the application software to be loaded into the inactive partition will have the address of the active partition. the bootloader firmware will need to offset the address by 0x400000 in order to write to the inactive partition. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 80 ? 2013-2015 microchip technology inc. 5.6 control registers five sfrs are used to write and erase the program flash memory: nvmcon, nvmkey, nvmadr, nvmadru and nvmsrcadr/h. the nvmcon register ( register 5-1 ) selects the operation to be performed (page erase, word/row program, inactive partition erase), initiates the program or erase cycle and is used to determine the active partition in dual partition modes. nvmkey ( register 5-4 ) is a write-only register that is used for write protection. to start a programming or erase sequence, the user application must consecutively write 0x55 and 0xaa to the nvmkey register. there are two nvm address registers: nvmadru and nvmadr. these two registers, when concatenated, form the 24-bit effective address (ea) of the selected word/row for programming operations, or the selected page for erase operations. the nvmadru register is used to hold the upper 8 bits of the ea, while the nvmadr register is used to hold the lower 16 bits of the ea. for row programming operation, data to be written to program flash memory is written into data memory space (ram) at an address defined by the nvmsrcadr register (location of first element in row programming data). downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 81 dspic33epxxgs50x family register 5-1: nvmcon: nonvolatil e memory (nvm) control register r/so-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 r/c-0 r-0 r/w-0 r/c-0 wr wren wrerr nvmsidl ( 2 ) sftswp ( 6 ) p2activ ( 6 ) rpdf urerr bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) n v m o p 3 ( 3 , 4 ) nvmop2 ( 3 , 4 ) nvmop1 ( 3 , 4 ) nvmop0 ( 3 , 4 ) bit 7 bit 0 legend: c = clearable bit so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 wr: write control bit ( 1 ) 1 = initiates a flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit ( 1 ) 1 = enables flash program/erase operations 0 = inhibits flash program/erase operations bit 13 wrerr: write sequence error flag bit ( 1 ) 1 = an improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12 nvmsidl: nvm stop in idle control bit ( 2 ) 1 = flash voltage regulator goes into standby mode during idle mode 0 = flash voltage regulator is active during idle mode bit 11 sftswp: partition soft swap status bit ( 6 ) 1 = partitions have been successfully swapped using the bootswp instruction (soft swap) 0 = awaiting successful partition swap using the bootswp instruction or a device reset will determine the active partition based on fbtseq bit 10 p2activ: partition 2 active status bit ( 6 ) 1 = partition 2 flash is mapped into the active region 0 = partition 1 flash is mapped into the active region bit 9 rpdf: row programming data format bit 1 = row data to be stored in ram in compressed format 0 = row data to be stored in ram in uncompressed format bit 8 urerr: row programming data underrun error bit 1 = indicates row programming operation has been terminated 0 = no data underrun error is detected bit 7-4 unimplemented: read as 0 note 1: these bits can only be reset on a por. 2: if this bit is set, power consumption will be further reduced (i idle ) and upon exiting idle mode, there is a delay (t vreg ) before flash memory becomes operational. 3: all other combinations of nvmop<3:0> are unimplemented. 4: execution of the pwrsav instruction is ignored while any of the nvm operations are in progress. 5: two adjacent words on a 4-word boundary are programmed during execution of this operation. 6: only available on dspic33ep64gs50x devices operating in dual partition mode. for all other devices, this bit is reserved. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 82 ? 2013-2015 microchip technology inc. bit 3-0 nvmop<3:0>: nvm operation select bits ( 1 , 3 , 4 ) 1111 = reserved 0101 = reserved 0100 = inactive partition memory erase operation 0011 = memory page erase operation 0010 = memory row program operation 0001 = memory double-word program operation ( 5 ) 0000 = reserved register 5-1: nvmcon: nonv olatile memory (nvm) cont rol register (continued) note 1: these bits can only be reset on a por. 2: if this bit is set, power consumption will be further reduced (i idle ) and upon exiting idle mode, there is a delay (t vreg ) before flash memory becomes operational. 3: all other combinations of nvmop<3:0> are unimplemented. 4: execution of the pwrsav instruction is ignored while any of the nvm operations are in progress. 5: two adjacent words on a 4-word boundary are programmed during execution of this operation. 6: only available on dspic33ep64gs50x devices operating in dual partition mode. for all other devices, this bit is reserved. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 83 dspic33epxxgs50x family register 5-2: nvmadr: nonvolatil e memory lower address register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadr<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 nvmadr<15:0>: nonvolatile memory lower write address bits selects the lower 16 bits of the location to program or erase in program flash memory. this register may be read or written to by the user application. register 5-3: nvmadru: nonvolatil e memory upper address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadru<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 nvmadru<23:16>: nonvolatile memory upper write address bits selects the upper 8 bits of the location to program or erase in program flash memory. this register may be read or written to by the user application. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 84 ? 2013-2015 microchip technology inc. register 5-4: nvmkey: nonvol atile memory key register register 5-5: nvmsrcadr: nvm source data address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 nvmkey<7:0>: nvm key register bits (write-only) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcadr<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 nvmsrcadr<15:0>: nvm source data address bits the ram address of the data to be programmed into flash when the nvmop<3:0> bits are set to row programming. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 85 dspic33epxxgs50x family 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: por: power-on reset bor: brown-out reset mclr : master clear pin reset swr: reset instruction wdto: watchdog timer time-out reset cm: configuration mismatch reset trapr: trap conflict reset iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst signal active. on system reset, some of the registers associated with the cpu and peripherals are forced to a known reset state, and some are unaffected. all types of device reset set a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). a por clears all the bits, except for the bor and por bits (rcon<1:0>) that are set. the user application can set or clear any bit, at any time, during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. for all resets, the default clock source is determined by the fnosc<2:0> bits in the foscsel configura- tion register. the value of the fnoscx bits is loaded into the nosc<2:0> (osccon<10:8>) bits on reset, which in turn, initializes the system clock. figure 6-1: reset sy stem block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to reset (ds70602) in the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ) 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: refer to the specific peripheral section or section 4.0 memory organization of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. mclr v dd bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch security reset internal regulator downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 86 ? 2013-2015 microchip technology inc. 6.1 reset resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 6.1.1 key resources reset (ds70602) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 87 dspic33epxxgs50x family register 6-1: rcon: re set control register ( 1 ) r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 trapr iopuwr v r e g s f c mv r e g s bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten ( 2 ) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w register access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w register reset has not occurred bit 13-12 unimplemented: read as 0 bit 11 vregsf: flash voltage regulator standby during sleep bit 1 = flash voltage regulator is active during sleep 0 = flash voltage regulator goes into standby mode during sleep bit 10 unimplemented: read as 0 bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred. 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit ( 2 ) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does n ot cause a device reset. 2: if the wdten<1:0> configuration bits are 11 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 88 ? 2013-2015 microchip technology inc. bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device has been in idle mode 0 = device has not been in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register ( 1 ) (continued) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does n ot cause a device reset. 2: if the wdten<1:0> configuration bits are 11 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 89 dspic33epxxgs50x family 7.0 interrupt controller the dspic33epxxgs50x family interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dspic33epxxgs50x family cpu. the interrupt controller has the following features: six processor exceptions and software traps seven user-selectable priority levels interrupt vector table (ivt) with a unique vector for each interrupt or exception source fixed priority within a specified user priority level fixed interrupt entry and return latencies alternate interrupt vector table (aivt) for debug support 7.1 interrupt vector table the dspic33epxxgs50x family interrupt vector table (ivt), shown in figure 7-1 , resides in program memory, starting at location, 000004h. the ivt contains six non-maskable trap vectors and up to 246 sources of interrupts. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt), shown in figure 7-2 , is available only when the boot segment is defined and the aivt has been enabled. to enable the alternate interrupt vector table, the configuration bit, aivtdis in the fsec register, must be programmed and the aivten bit must be set (intcon2<8> = 1 ). when the aivt is enabled, all interrupt and exception processes use the alternate vectors instead of the default vectors. the aivt begins at the start of the last page of the boot segment, defined by bslim<12:0>. the second half of the page is no longer usable space. the boot segment must be at least 2 pages to enable the aivt. the aivt supports debugging by providing a means to switch between an application and a support environ- ment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. 7.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the dspic33epxxgs50x family devices clear their registers in response to a reset, which forces the pc to zero. the device then begins program execution at location, 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to interrupts (ds70000600) in the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: although the boot segment must be enabled in order to enable the aivt, application code does not need to be present inside of the boot segment. the aivt (and ivt) will inherit the boot segment code protection. note: any unimplemented or unused vector locations in the ivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 90 ? 2013-2015 microchip technology inc. figure 7-1: dspic33epxxgs50x fa mily interrupt vector table ivt decreasing natural order priority reset C goto instruction 0x000000 reset C goto address 0x000002 oscillator fail trap vector 0x000004 address error trap vector 0x000006 generic hard trap vector 0x000008 stack error trap vector 0x00000a math error trap vector 0x00000c reserved 0x00000e generic soft trap vector 0x000010 reserved 0x000012 interrupt vector 0 0x000014 interrupt vector 1 0x000016 :::: :: interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 :::: :: interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe interrupt vector 118 0x000100 interrupt vector 119 0x000102 interrupt vector 120 0x000104 :::: :: interrupt vector 244 0x0001fc interrupt vector 245 0x0001fe start of code 0x000200 see ta b l e 7 - 1 for interrupt vector details note: in dual partition modes, each partition has a dedicated interrupt vector table. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 91 dspic33epxxgs50x family figure 7-2: dspic33epxxgs50x alternate interrupt vector table ( 2 ) note 1: the address depends on the size of the boot segment defined by bslim<12:0>. [(bslim<12:0> C 1) x 0x400] + offset. 2: in dual partition modes, each partition has a dedicated alternate interrupt vector table (if enabled). aivt decreasing natural order priority reserved bslim<12:0> ( 1 ) + 0x000000 reserved bslim<12:0> ( 1 ) + 0x000002 oscillator fail trap vector bslim<12:0> ( 1 ) + 0x000004 address error trap vector bslim<12:0> ( 1 ) + 0x000006 generic hard trap vector bslim<12:0> ( 1 ) + 0x000008 stack error trap vector bslim<12:0> ( 1 ) + 0x00000a math error trap vector bslim<12:0> ( 1 ) + 0x00000c reserved bslim<12:0> ( 1 ) + 0x00000e generic soft trap vector bslim<12:0> ( 1 ) + 0x000010 reserved bslim<12:0> ( 1 ) + 0x000012 interrupt vector 0 bslim<12:0> ( 1 ) + 0x000014 interrupt vector 1 bslim<12:0> ( 1 ) + 0x000016 :::: :: interrupt vector 52 bslim<12:0> ( 1 ) + 0x00007c interrupt vector 53 bslim<12:0> ( 1 ) + 0x00007e interrupt vector 54 bslim<12:0> ( 1 ) + 0x000080 :::: :: interrupt vector 116 bslim<12:0> ( 1 ) + 0x0000fc interrupt vector 117 bslim<12:0> ( 1 ) + 0x0000fe interrupt vector 118 bslim<12:0> ( 1 ) + 0x000100 interrupt vector 119 bslim<12:0> ( 1 ) + 0x000102 interrupt vector 120 bslim<12:0> ( 1 ) + 0x000104 :::: :: interrupt vector 244 bslim<12:0> ( 1 ) + 0x0001fc interrupt vector 245 bslim<12:0> ( 1 ) + 0x0001fe see tab l e 7 - 1 for interrupt vector details downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 92 ? 2013-2015 microchip technology inc. table 7-1: interrupt vector details interrupt source vector # irq # ivt address interrupt bit location flag enable priority highest natural order priority int0 C external interrupt 0 8 0 0x000014 ifs0<0> iec0<0> ipc0<2:0> ic1 C input capture 1 9 1 0x000016 ifs0<1> iec0<1> ipc0<6:4> oc1 C output compare 1 10 2 0x000018 ifs0<2> iec0<2> ipc0<10:8> t1 C timer1 11 3 0x00001a ifs0<3> iec0<3> ipc0<14:12> reserved 12 4 0x00001c ic2 C input capture 2 13 5 0x00001e ifs0<5> iec0<5> ipc1<6:4> oc2 C output compare 2 14 6 0x000020 ifs0<6> iec0<6> ipc1<10:8> t2 C timer2 15 7 0x000022 ifs0<7> iec0<7> ipc1<14:12> t3 C timer3 16 8 0x000024 ifs0<8> iec0<8> ipc2<2:0> spi1e C spi1 error 17 9 0x000026 ifs0<9> iec0<9> ipc2<6:4> spi1 C spi1 transfer done 18 10 0x000028 ifs0<10> iec0<10> ipc2<10:8> u1rx C uart1 receiver 19 11 0x00002a ifs0<11> iec0<11> ipc2<14:12> u1tx C uart1 transmitter 20 12 0x00002c ifs0<12> iec0<12> ipc3<2:0> adc C adc global convert done 21 13 0x00002e ifs0<13> iec0<13> ipc3<6:4> reserved 22 14 0x000030 nvm C nvm write complete 23 15 0x000032 ifs0<15> iec0<15> ipc3<14:12> si2c1 C i2c1 slave event 24 16 0x000034 ifs1<0> iec1<0> ipc4<2:0> mi2c1 C i2c1 master event 25 17 0x000036 ifs1<1> iec1<1> ipc4<6:4> cmp1 C analog comparator 1 interrupt 26 18 0x000038 ifs1<2> iec1<2> ipc4<10:8> cn C input change interrupt 27 19 0x00003a ifs1<3> iec1<3> ipc4<14:12> int1 C external interrupt 1 28 20 0x00003c ifs1<4> iec1<4> ipc5<2:0> reserved 29-32 21-24 0x00003e-0x000044 oc3 C output compare 3 33 25 0x000046 ifs1<9> iec1<9> ipc6<6:4> oc4 C output compare 4 34 26 0x000048 ifs1<10> iec1<10> ipc6<10:8> t4 C timer4 35 27 0x00004a ifs1<11> iec1<11> ipc6<14:12> t5 C timer5 36 28 0x00004c ifs1<12> iec1<12> ipc7<2:0> int2 C external interrupt 2 37 29 0x00004e ifs1<13> iec1<13> ipc7<6:4> u2rx C uart2 receiver 38 30 0x000050 ifs1<14> iec1<14> ipc7<10:8> u2tx C uart2 transmitter 39 31 0x000052 ifs1<15> iec1<15> ipc7<14:12> spi2e C spi2 error 40 32 0x000054 ifs2<0> iec2<0> ipc8<2:0> spi2 C spi2 transfer done 41 33 0x000056 ifs2<1> iec2<1> ipc8<6:4> reserved 42-44 34-36 0x000058-0x00005c ic3 C input capture 3 45 37 0x00005e ifs2<5> iec2<5> ipc9<6:4> ic4 C input capture 4 46 38 0x000060 ifs2<6> iec2<6> ipc9<10:8> reserved 47-56 39-48 0x000062-0x000074 si2c2 C i2c2 slave event 57 49 0x000076 ifs3<1> iec3<1> ipc12<6:4> mi2c2 C i2c2 master event 58 50 0x000078 ifs3<2> iec3<2> ipc12<10:8> reserved 59-61 51-53 0x00007a-0x00007e int4 C external interrupt 4 62 54 0x000080 ifs3<6> iec3<6> ipc13<10:8> reserved 63-64 55-54 0x000082-0x000084 psem C pwm special event match 65 57 0x000086 ifs3<9> iec3<9> ipc14<6:4> reserved 66-72 58-64 0x000088-0x000094 u1e C uart1 error interrupt 73 65 0x000096 ifs4<1> iec4<1> ipc16<6:4> u2e C uart2 error interrupt 74 66 0x000098 ifs4<2> iec4<2> ipc16<10:8> reserved 75-80 67-72 0x00009a-0x0000a4 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 93 dspic33epxxgs50x family pwm secondary special event match 81 73 0x0000a6 ifs4<9> iec4<9> ipc18<6:4> reserved 82-101 74-93 0x0000a8-0x0000ce pwm1 C pwm1 interrupt 102 94 0x0000d0 ifs5<14> iec5<14> ipc23<10:8> pwm2 C pwm2 interrupt 103 95 0x0000d2 ifs5<15> iec5<15> ipc23<14:12> pwm3 C pwm3 interrupt 104 96 0x0000d4 ifs6<0> iec6<0> ipc24<2:0> pwm4 C pwm4 interrupt 105 97 0x0000d6 ifs6<1> iec6<1> ipc24<6:4> pwm5 C pwm5 interrupt 106 98 0x0000d8 ifs6<2> iec6<2> ipc24<10:8> reserved 106-110 99-102 0x0000da-0x0000e0 cmp2 C analog comparator 2 interrupt 111 103 0x0000e2 ifs6<7> iec6<7> ipc25<14:12> cmp3 C analog comparator 3 interrupt 112 104 0x0000e4 ifs6<8> iec6<8> ipc26<2:0> cmp4 C analog comparator 4 interrupt 113 105 0x0000e6 ifs6<9> iec6<9> ipc26<6:4> reserved 114-117 106-109 0x0000e8-0x0000ee an0 conversion done 118 110 0x0000f0 ifs6<14> iec6<14> ipc27<10:8> an1 conversion done 119 111 0x0000f2 ifs6<15> iec6<15> ipc27<14:12> an2 conversion done 120 112 0x0000f4 ifs7<0> iec7<0> ipc28<2:0> an3 conversion done 121 113 0x0000f6 ifs7<1> iec7<1> ipc28<6:4> an4 conversion done 122 114 0x0000f8 ifs7<2> iec7<2> ipc28<10:8> an5 conversion done 123 115 0x0000fa ifs7<3> iec7<3> ipc28<14:12> an6 conversion done 124 116 0x0000fc ifs7<4> iec7<4> ipc29<2:0> an7 conversion done 125 117 0x0000fe ifs7<5> iec7<5> ipc29<6:4> reserved 126-149 118-141 0x000100-0x00012e icd C icd application 150 142 0x000130 ifs8<14> iec8<14> ipc35<10:8> jtag C jtag programming 151 143 0x000132 ifs8<15> iec8<15> ipc35<14:12> reserved 152-158 144-150 0x000134-0x000140 an8 conversion done 159 151 0x000142 ifs9<7> iec9<7> ipc37<14:12> an9 conversion done 160 152 0x000144 ifs9<8> iec9<8> ipc38<2:0> an10 conversion done 161 153 0x000146 ifs9<9> iec9<9> ipc38<6:4> an11 conversion done 162 154 0x000148 ifs9<10> iec9<10> ipc38<10:8> an12 conversion done 163 155 0x00014a ifs9<11> iec9<11> ipc38<14:12> an13 conversion done 164 156 0x00014c ifs9<12> iec9<12> ipc39<2:0> an14 conversion done 165 157 0x00014e ifs9<13> iec9<13> ipc39<6:4> an15 conversion done 166 158 0x000150 ifs9<14> iec9<14> ipc39<10:8> an16 conversion done 167 159 0x000152 ifs9<15> iec9<15> ipc39<14:12> an17 conversion done 168 160 0x000154 ifs10<0> iec10<0> ipc40<2:0> an18 conversion done 169 161 0x000156 ifs10<1> iec10<1> ipc40<6:4> an19 conversion done 170 162 0x000158 ifs10<2> iec10<2> ipc40<10:8> an20 conversion done 171 163 0x00015a ifs10<3> iec10<3> ipc40<14:12> an21 conversion done 172 164 0x00015c ifs10<4> iec10<4> ipc41<2:0> reserved 173-180 165-172 0x00015c-0x00016c i2c1 C i2c1 bus collision 181 173 0x00016e ifs10<13> iec10<13> ipc43<6:4> i2c2 C i2c2 bus collision 182 174 0x000170 ifs10<14> iec10<14> ipc43<10:8 > reserved 183-184 175-176 0x000172-0x000174 adcmp0 C adc digital comparator 0 185 177 0x000176 ifs11<1> iec11<1> ipc 44<6:4> adcmp1 C adc digital comparator 1 186 178 0x000178 ifs11<2> iec11<2> ipc 44<10:8> adfltr0 C adc filter 0 187 179 0x00017a ifs11<3> iec11<3> ipc44<14:12> adfltr1 C adc filter 1 188 180 0x00017c ifs11<4> iec11<4> ipc45<2:0> reserved 189-253 181-245 0x00017e-0x0001fe table 7-1: interrupt vector details (continued) interrupt source vector # irq # ivt address interrupt bit location flag enable priority downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 94 ? 2013-2015 microchip technology inc. 7.3 interrupt resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 7.3.1 key resources interrupts (ds70000600) in the dspic33/ pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools 7.4 interrupt control and status registers dspic33epxxgs50x family devices implement the following registers for the interrupt controller: intcon1 intcon2 intcon3 intcon4 inttreg 7.4.1 intcon1 through intcon4 global interrupt control functions are controlled from intcon1, intcon2, intcon3 and intcon4. intcon1 contains the interrupt nesting disable bit (nstdis), as well as the control and status flags for the processor trap sources. the intcon2 register controls external interrupt request signal behavior, contains the global interrupt enable bit (gie) and the alternate interrupt vector table enable bit (aivten). intcon3 contains the status flags for the auxiliary pll and do stack overflow status trap sources. the intcon4 register contains the software generated hard trap status bit (sght). 7.4.2 ifsx the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.4.3 iecx the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.4.4 ipcx the ipcx registers are used to set the interrupt priority level (ipl) for each source of interrupt. each user interrupt sources can be assigned to one of seven priority levels. 7.4.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into the vector number (vecnum<7:0>) and interrupt level bits (ilr<3:0>) fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence as they are listed in table 7-1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0> and the int0ip<2:0> bits in the first position of ipc0 (ipc0<2:0>). 7.4.6 status/control registers although these registers are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality. for more information on these registers refer to cpu (ds70359) in the dspic33/pic24 family reference manual . the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user software can change the current cpu interrupt priority level by writing to the iplx bits. the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-3 through register 7-7 in the following pages. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 95 dspic33epxxgs50x family register 7-1: sr: cpu status register ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/c-0 r/c-0 r-0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 ( 3 ) r/w-0 ( 3 ) r/w-0 ( 3 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 2 ) ipl1 ( 2 ) ipl0 ( 2 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1= bit is set 0 = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 2 , 3 ) 111 = cpu interrupt priority level is 7 (15); user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1 . 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when the nstdis bit (intcon1<15>) = 1 . downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 96 ? 2013-2015 microchip technology inc. register 7-2: corcon: core control register ( 1 ) r/w-0 u-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 var us1 us0 edt dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) sfa rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1= bit is set 0 = bit is cleared x = bit is unknown bit 15 var: variable exception processing latency control bit 1 = variable exception processing is enabled 0 = fixed exception processing is enabled bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 97 dspic33epxxgs50x family register 7-3: intcon1: in terrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr div0err matherr addrerr stkerr oscfail bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit 1 = trap overflow of accumulator a 0 = trap is disabled bit 9 ovbte: accumulator b overflow trap enable bit 1 = trap overflow of accumulator b 0 = trap is disabled bit 8 covte: catastrophic overflow trap enable bit 1 = trap on catastrophic overflow of accumulator a or b is enabled 0 = trap is disabled bit 7 sftacerr: shift accumulator error status bit 1 = math error trap was caused by an invalid accumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: divide-by-zero error status bit 1 = math error trap was caused by a divide-by-zero 0 = math error trap was not caused by a divide-by-zero bit 5 unimplemented: read as 0 bit 4 matherr: math error status bit 1 = math error trap has occurred 0 = math error trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 98 ? 2013-2015 microchip technology inc. bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as 0 register 7-3: intcon1: interrupt control register 1 (continued) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 99 dspic33epxxgs50x family register 7-4: intcon2: in terrupt control register 2 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 gie disi swtrap a i v t e n bit 15 bit 8 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 i n t 4 e p int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 gie: global interrupt enable bit 1 = interrupts and associated ie bits are enabled 0 = interrupts are disabled, but traps are still enabled bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13 swtrap: software trap status bit 1 = software trap is enabled 0 = software trap is disabled bit 12-9 unimplemented: read as 0 bit 8 aivten: alternate interrupt vector table enable 1 = uses alternate interrupt vector table 0 = uses standard interrupt vector table bit 7-5 unimplemented: read as 0 bit 4 int4ep: external interrupt 4 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 3 unimplemented: read as 0 bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 100 ? 2013-2015 microchip technology inc. register 7-5: intcon3: in terrupt control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 n a e bit 15 bit 8 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 d o o v r a p l l bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as 0 bit 8 nae: nvm address error soft trap status bit 1 = nvm address error soft trap has occurred 0 = nvm address error soft trap has not occurred bit 7-5 unimplemented: read as 0 bit 4 doovr: do stack overflow soft trap status bit 1 = do stack overflow soft trap has occurred 0 = do stack overflow soft trap has not occurred bit 3-1 unimplemented: read as 0 bit 0 apll: auxiliary pll loss of lock soft trap status bit 1 = apll lock soft trap has occurred 0 = apll lock soft trap has not occurred register 7-6: intcon4: in terrupt control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 s g h t bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-1 unimplemented: read as 0 bit 0 sght: software generated hard trap status bit 1 = software generated hard trap has occurred 0 = software generated hard trap has not occurred downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 101 dspic33epxxgs50x family register 7-7: inttreg: interrupt control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ilr3 ilr2 ilr1 ilr0 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 vecnum7 vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7-0 vecnum<7:0>: vector number of pending interrupt bits 11111111 = 255, reserved; do not use 00001001 = 9, ic1 C input capture 1 00001000 = 8, int0 C external interrupt 0 00000111 = 7, reserved; do not use 00000110 = 6, generic soft error trap 00000101 = 5, reserved; do not use 00000100 = 4, math error trap 00000011 = 3, stack error trap 00000010 = 2, generic hard trap 00000001 = 1, address error trap 00000000 = 0, oscillator fail trap downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 102 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 103 dspic33epxxgs50x family 8.0 oscillator configuration the dspic33epxxgs50x family oscillator system provides: on-chip phase-locked loop (pll) to boost internal operating frequency on select internal and external oscillator sources on-the-fly clock switching between various clock sources doze mode for system power savings fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown configuration bits for clock source selection auxiliary pll for adc and pwm a simplified diagram of the oscillator system is shown in figure 8-1 . note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to oscillator module (ds70005131) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 104 ? 2013-2015 microchip technology inc. figure 8-1: oscillator system diagram xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, frcdivn frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset lprc oscillator doze<2:0> s3s1 s2 s1/s3 s7 s6 frc lprc s0s5 clock switch s0 clock fail 2 tun<5:0> pll f cy (2) f osc frcdiv doze note 1: see figure 8-2 for the source of the f vco signal. 2: f p refers to the clock source for all the peripherals, while f cy (or mips) refers to the clock source for the cpu. throughout this document, f cy and f p are used interchangeably, except in the case of doze mode. f p and f cy will be different when doze mode is used in any ratio other than 1:1. 3: the auxiliary clock postscaler must be configured to divide-by-1 (apstsclr<2:0> = 111 ) for proper operation of the pwm and adc modules. fscm aclk poscclk selaclk f vco (1) asrcsel enapll apll x 16 poscclk frcclk f vco (1) n apstsclr<2:0> (4) frcclk frcsel osc2 osc1 primary oscillator (posc) poscmd<1:0> f p (2) auxiliary clock generator circuit block diagram 10 10 1 0 01 gnd pwm/adc reference clock output poscclk rosel f osc n rpn refclko rodiv<3:0> to lfsr 16 f pllo frc oscillator downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 105 dspic33epxxgs50x family 8.1 cpu clocking system the dspic33epxxgs50x family of devices provides six system clock options: fast rc (frc) oscillator frc oscillator with phase-locked loop (pll) frc oscillator with postscaler primary (xt, hs or ec) oscillator primary oscillator with pll low-power rc (lprc) oscillator instruction execution speed or device operating frequency, f cy , is given by equation 8-1 . equation 8-1: device operating frequency figure 8-2 is a block diagram of the pll module. equation 8-2 provides the relationship between input frequency (f in ) and output frequency (f pllo ). equation 8-3 provides the relationship between input frequency (f in ) and vco frequency (f vco ). figure 8-2: pll block diagram equation 8-2: f pllo calculation equation 8-3: f vco calculation f cy = f osc /2 n1 m n2 pfd vco pllpre<4:0> plldiv<8:0> pllpost<1:0> 0.8 mhz < f plli (1) < 8.0 mhz 120 mh z < f vco (1) < 340 mh z f pllo (1) ? 120 mhz @ +125oc f in f plli f vco f osc note 1: this frequency range must be met at all times. f pllo (1) ? 140 mhz @ +85oc where: n 1 = pllpre <4:0> + 2 n 2 = 2 x ( pllpost <1:0> + 1) m = plldiv <8:0> + 2 f pllo = f in ? plldiv <8:0> + 2 ( pllpre <4:0> + 2) ?? 2( pllpost <1:0> + 1) m n 1 ?? ? ? () () = f in ? f vco = f in ? plldiv <8:0> + 2 ( pllpre <4:0> + 2) m n 1 () () = f in ? downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 106 ? 2013-2015 microchip technology inc. table 8-1: configuration bit va lues for clock selection 8.2 auxiliary clock generation the auxiliary clock generation is used for peripherals that need to operate at a frequency unrelated to the system clock, such as pwm or adc. the primary oscillator and internal frc oscillator sources can be used with an auxiliary pll (apll) to obtain the auxiliary clock. the auxiliary pll has a fixed 16x multiplication factor. the auxiliary clock has the following configuration restrictions: for proper pwm operation, auxiliary clock generation must be configured for 120 mhz (see parameter os56 in section 26.0 electrical char- acteristics ). if a slower frequency is desired, the pwm input clock prescaler (divider) select bits (pclkdiv<2:0>) should be used. to achieve 1.04 ns pwm resolution, the auxiliary clock must use the 16x auxiliary pll (apll). all other clock sources will have a minimum pwm resolution of 8 ns. if the primary pll is used as a source for the auxiliary clock, the primary pll should be config- ured up to a maximum operation of 30 mips or less. 8.3 reference clock generation the reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. the user application can specify a wide range of clock scaling prior to outputting the reference clock. 8.4 oscillator resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 8.4.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools oscillator mode oscillator source poscmd<1:0> fnosc<2:0> see notes fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1 , 2 fast rc oscillator with divide-by-16 internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 primary oscillator (hs) with pll (hspll) primary 10 011 primary oscillator (xt) with pll (xtpll) primary 01 011 primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 1 fast rc oscillator (frc) with divide-by-n and pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 107 dspic33epxxgs50x family 8.5 oscillator control registers register 8-1: osccon: os cillator control register ( 1 ) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y cosc2 cosc1 cosc0 n o s c 2 ( 2 ) nosc1 ( 2 ) nosc0 ( 2 ) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/w-0 u-0 u-0 r/w-0 clklock iolock lock c f ( 3 ) oswen bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = reserved 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcpll) 000 = fast rc oscillator (frc) bit 11 unimplemented: read as 0 bit 10-8 nosc<2:0>: new oscillator selection bits ( 2 ) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = reserved 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcpll) 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit 1 = if (fcksm0 = 1 ), then clock and pll configurations are locked; if (fcksm0 = 0 ), then clock and pll configurations may be modified 0 = clock and pll selections are not locked, configurations may be modified bit 6 iolock: i/o lock enable bit 1 = i/o lock is active 0 = i/o lock is not active bit 5 lock: pll lock status bit (read-only) 1 = indicates that pll is in lock or pll start-up timer is satisfied 0 = indicates that pll is out of lock, start-up timer is in progress or pll is disabled note 1: writes to this register require an unlock sequence. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switc h to frc mode as a transitional clock source between the two pll modes. 3: this bit should only be cleared in software. setting the bit in software (= 1 ) will have the same effect as an actual oscillator failure and will trigger an oscillator failure trap. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 108 ? 2013-2015 microchip technology inc. bit 4 unimplemented: read as 0 bit 3 cf: clock fail detect bit ( 3 ) 1 = fscm has detected a clock failure 0 = fscm has not detected a clock failure bit 2-1 unimplemented: read as 0 bit 0 oswen: oscillator switch enable bit 1 = requests oscillator switch to the selection specified by the nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register ( 1 ) (continued) note 1: writes to this register require an unlock sequence. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switc h to frc mode as a transitional clock source between the two pll modes. 3: this bit should only be cleared in software. setting the bit in software (= 1 ) will have the same effect as an actual oscillator failure and will trigger an oscillator failure trap. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 109 dspic33epxxgs50x family register 8-2: clkdiv: clock divisor register r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze2 ( 1 ) doze1 ( 1 ) doze0 ( 1 ) dozen ( 2 , 3 ) frcdiv2 frcdiv1 frcdiv0 bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost1 pllpost0 pllpre4 pllpre3 pllpre2 pllpre1 pllpre0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the processor clock, and the peripheral cloc k ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits ( 1 ) 111 = f cy divided by 128 110 = f cy divided by 64 101 = f cy divided by 32 100 = f cy divided by 16 011 = f cy divided by 8 (default) 010 = f cy divided by 4 001 = f cy divided by 2 000 = f cy divided by 1 bit 11 dozen: doze mode enable bit ( 2 , 3 ) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock and peripheral clock ratio is forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc oscillator postscaler bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 000 = frc divided by 1 (default) bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as n2, pll postscaler) 11 = output divided by 8 10 = reserved 01 = output divided by 4 (default) 00 = output divided by 2 bit 5 unimplemented: read as 0 note 1: the doze<2:0> bits can only be written to when the dozen bit is clear. if dozen = 1 , any writes to doze<2:0> are ignored. 2: this bit is cleared when the roi bit is set and an interrupt occurs. 3: the dozen bit cannot be set if doze<2:0> = 000 . if doze<2:0> = 000 , any attempt by user software to set the dozen bit is ignored. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 110 ? 2013-2015 microchip technology inc. bit 4-0 pllpre<4:0>: pll phase detector input divider select bits (also denoted as n1, pll prescaler) 11111 = input divided by 33 00001 = input divided by 3 00000 = input divided by 2 (default) register 8-2: clkdiv: clock divisor register (continued) note 1: the doze<2:0> bits can only be written to when the dozen bit is clear. if dozen = 1 , any writes to doze<2:0> are ignored. 2: this bit is cleared when the roi bit is set and an interrupt occurs. 3: the dozen bit cannot be set if doze<2:0> = 000 . if doze<2:0> = 000 , any attempt by user software to set the dozen bit is ignored. register 8-3: pllfbd: p ll feedback divisor register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 plldiv8 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as 0 bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as m, pll multiplier) 111111111 = 513 000110000 = 50 (default) 000000010 = 4 000000001 = 3 000000000 = 2 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 111 dspic33epxxgs50x family register 8-4: osctun: frc oscillator tuning register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t u n < 5 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 tun<5:0>: frc oscillator tuning bits 011111 = maximum frequency deviation of 1.457% (7.477 mhz) 011110 = center frequency + 1.41% (7.474 mhz) 000001 = center frequency + 0.047% (7.373 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency C 0.047% (7.367 mhz) 100001 = center frequency C 1.457% (7.263 mhz) 100000 = minimum frequency deviation of -1.5% (7.259 mhz) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 112 ? 2013-2015 microchip technology inc. register 8-5: aclkcon: auxiliary clock divisor control register r/w-0 r-0 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 enapll apllck selaclk apstsclr2 apstsclr1 apstsclr0 bit 15 bit 8 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 asrcsel frcsel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 enapll: auxiliary pll enable bit 1 = apll is enabled 0 = apll is disabled bit 14 apllck: apll locked status bit (read-only) 1 = indicates that auxiliary pll is in lock 0 = indicates that auxiliary pll is not in lock bit 13 selaclk: select auxiliary clock source for auxiliary clock divider bit 1 = auxiliary oscillators provide the source clock for the auxiliary clock divider 0 = primary pll (f vco ) provides the source clock for the auxiliary clock divider bit 12-11 unimplemented: read as 0 bit 10-8 apstsclr<2:0>: auxiliary clock output divider bits 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 bit 7 asrcsel: select reference clock source for auxiliary clock bit 1 = primary oscillator is the clock source 0 = no clock input is selected bit 6 frcsel: select reference clock source for auxiliary pll bit 1 = selects the frc clock for auxiliary pll 0 = input clock source is determined by the asrcsel bit setting bit 5-0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 113 dspic33epxxgs50x family register 8-6: refocon: reference oscillator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 roon rosslp rosel rodiv3 ( 1 ) rodiv2 ( 1 ) rodiv1 ( 1 ) rodiv0 ( 1 ) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 roon: reference oscillator output enable bit 1 = reference oscillator output is enabled on the rpn pin ( 2 ) 0 = reference oscillator output is disabled bit 14 unimplemented: read as 0 bit 13 rosslp: reference oscillator run in sleep bit 1 = reference oscillator output continues to run in sleep 0 = reference oscillator output is disabled in sleep bit 12 rosel: reference oscillator source select bit 1 = oscillator crystal is used as the reference clock 0 = system clock is used as the reference clock bit 11-8 rodiv<3:0>: reference oscillator divider bits ( 1 ) 1111 = reference clock divided by 32,768 1110 = reference clock divided by 16,384 1101 = reference clock divided by 8,192 1100 = reference clock divided by 4,096 1011 = reference clock divided by 2,048 1010 = reference clock divided by 1,024 1001 = reference clock divided by 512 1000 = reference clock divided by 256 0111 = reference clock divided by 128 0110 = reference clock divided by 64 0101 = reference clock divided by 32 0100 = reference clock divided by 16 0011 = reference clock divided by 8 0010 = reference clock divided by 4 0001 = reference clock divided by 2 0000 = reference clock bit 7-0 unimplemented: read as 0 note 1: the reference oscillator output must be disabled (roon = 0 ) before writing to these bits. 2: this pin is remappable. see section 10.4 peripheral pin select (pps) for more information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 114 ? 2013-2015 microchip technology inc. register 8-7: lfsr: linear feedback shift register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 l f s r < 1 4 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lfsr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-0 lfsr<14:0>: pseudorandom data bits downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 115 dspic33epxxgs50x family 9.0 power-saving features the dspic33epxxgs50x family devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of peripherals being clocked constitutes lower consumed power. dspic33epxxgs50x family devices can manage power consumption in four ways: clock frequency instruction-based sleep and idle modes software-controlled doze mode selective peripheral control in software combinations of these methods can be used to selectively tailor an applications power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 clock frequency and clock switching the dspic33epxxgs50x family devices allow a wide range of clock frequencies to be selected under appli- cation control. if the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the noscx bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 8.0 oscillator configuration . 9.2 instruction-based power-saving modes the dspic33epxxgs50x family devices have two special power-saving modes that are entered through the execution of a special pwrsav instruc- tion. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 9-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake-up. example 9-1: pwrsav instruction syntax note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to watchdog timer and power-saving modes (ds70615) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: sleep_mode and idle_mode are con- stants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 116 ? 2013-2015 microchip technology inc. 9.2.1 sleep mode the following occurs in sleep mode: the system clock source is shut down. if an on-chip oscillator is used, it is turned off. the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current. the fail-safe clock monitor does not operate, since the system clock source is disabled. the lprc clock continues to run in sleep mode if the wdt is enabled. the wdt, if enabled, is automatically cleared prior to entering sleep mode. some device features or peripherals can continue to operate. this includes items such as the input change notification on the i/o ports or peripherals that use an external clock input. any peripheral that requires the system clock source for its operation is disabled. the device wakes up from sleep mode on any of the these events: any interrupt source that is individually enabled any form of device reset a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source that was active when sleep mode was entered. for optimal power savings, the internal regulator and the flash regulator can be configured to go into stand- by when sleep mode is entered by clearing the vregs (rcon<8>) and vregsf (rcon<11>) bits (default configuration). if the application requires a faster wake-up time, and can accept higher current requirements, the vregs (rcon<8>) and vregsf (rcon<11>) bits can be set to keep the internal regulator and the flash regulator active during sleep mode. 9.2.2 idle mode the following occurs in idle mode: the cpu stops executing instructions. the wdt is automatically cleared. the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 9.4 peripheral module disable ). if the wdt or fscm is enabled, the lprc also remains active. the device wakes from idle mode on any of these events: any interrupt that is individually enabled any device reset a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the pwrsav instruction or the first instruction in the isr. all peripherals also have the option to discontinue operation when idle mode is entered to allow for increased power savings. this option is selectable in the control register of each peripheral (for example, the tsidl bit in the timer1 control register (t1con<13>). 9.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 117 dspic33epxxgs50x family 9.3 doze mode the preferred strategies for reducing power consump- tion are changing clock speed and invoking one of the power-saving modes. in some circumstances, this cannot be practical. for example, it may be necessary for an application to maintain uninterrupted synchro- nous communication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configu- rations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an inter- rupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. 9.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers do not have any effect and read values are invalid. a peripheral module is enabled only if both the associ- ated bit in the pmd register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. 9.5 power-saving resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 9.5.1 key resources watchdog timer and power-saving modes (ds70615) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools note: if a pmd bit is set, the corresponding module is disabled after a delay of one instruction cycle. similarly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 118 ? 2013-2015 microchip technology inc. register 9-1: pmd1: peripheral mo dule disable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 t5md t4md t3md t2md t1md pwmmd bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 i2c1md u2md u1md spi2md spi1md adcmd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 t5md: timer5 module disable bit 1 = timer5 module is disabled 0 = timer5 module is enabled bit 14 t4md: timer4 module disable bit 1 = timer4 module is disabled 0 = timer4 module is enabled bit 13 t3md: timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md: timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md: timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10 unimplemented: read as 0 bit 9 pwmmd: pwmx module disable bit 1 = pwmx module is disabled 0 = pwmx module is enabled bit 8 unimplemented: read as 0 bit 7 i2c1md: i2c1 module disable bit 1 = i2c1 module is disabled 0 = i2c1 module is enabled bit 6 u2md: uart2 module disable bit 1 = uart2 module is disabled 0 = uart2 module is enabled bit 5 u1md: uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 spi2md: spi2 module disable bit 1 = spi2 module is disabled 0 = spi2 module is enabled bit 3 spi1md: spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2-1 unimplemented: read as 0 bit 0 adcmd: adc module disable bit 1 = adc module is disabled 0 = adc module is enabled downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 119 dspic33epxxgs50x family register 9-2: pmd2: peripheral mo dule disable control register 2 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ic4md ic3md ic2md ic1md bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 oc4md oc3md oc2md oc1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11 ic4md: input capture 4 module disable bit 1 = input capture 4 module is disabled 0 = input capture 4 module is enabled bit 10 ic3md: input capture 3 module disable bit 1 = input capture 3 module is disabled 0 = input capture 3 module is enabled bit 9 ic2md: input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md: input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7-4 unimplemented: read as 0 bit 3 oc4md: output compare 4 module disable bit 1 = output compare 4 module is disabled 0 = output compare 4 module is enabled bit 2 oc3md: output compare 3 module disable bit 1 = output compare 3 module is disabled 0 = output compare 3 module is enabled bit 1 oc2md: output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md: output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 120 ? 2013-2015 microchip technology inc. register 9-3: pmd3: peripheral mo dule disable control register 3 register 9-4: pmd4: peripheral mo dule disable control register 4 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 cmpmd bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 i2c2md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10 cmpmd: comparator module disable bit 1 = comparator module is disabled 0 = comparator module is enabled bit 9-2 unimplemented: read as 0 bit 1 i2c2md: i2c2 module disable bit 1 = i2c2 module is disabled 0 = i2c2 module is enabled bit 0 unimplemented: read as 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r e f o m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as 0 bit 3 refomd: reference clock module disable bit 1 = reference clock module is disabled 0 = reference clock module is enabled bit 2-0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 121 dspic33epxxgs50x family register 9-5: pmd6: peripheral mo dule disable control register 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwm5md pwm4md pwm3md pwm2md pwm1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 pwm5md: pwm5 module disable bit 1 = pwm5 module is disabled 0 = pwm5 module is enabled bit 11 pwm4md: pwm4 module disable bit 1 = pwm4 module is disabled 0 = pwm4 module is enabled bit 10 pwm3md: pwm3 module disable bit 1 = pwm3 module is disabled 0 = pwm3 module is enabled bit 9 pwm2md: pwm2 module disable bit 1 = pwm2 module is disabled 0 = pwm2 module is enabled bit 8 pwm1md: pwm1 module disable bit 1 = pwm1 module is disabled 0 = pwm1 module is enabled bit 7-0 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 122 ? 2013-2015 microchip technology inc. register 9-6: pmd7: peripheral mo dule disable control register 7 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cmp4md cmp3md cmp2md cmp1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 p g a 1 m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11 cmp4md: cmp4 module disable bit 1 = cmp4 module is disabled 0 = cmp4 module is enabled bit 10 cmp3md: cmp3 module disable bit 1 = cmp3 module is disabled 0 = cmp3 module is enabled bit 9 cmp2md: cmp2 module disable bit 1 = cmp2 module is disabled 0 = cmp2 module is enabled bit 8 cmp1md: cmp1 module disable bit 1 = cmp1 module is disabled 0 = cmp1 module is enabled bit 7-2 unimplemented: read as 0 bit 1 pga1md: pga1 module disable bit 1 = pga1 module is disabled 0 = pga1 module is enabled bit 0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 123 dspic33epxxgs50x family register 9-7: pmd8: peripheral mo dule disable control register 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 pga2md abgmd bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 c c s m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10 pga2md: pga2 module disable bit 1 = pga2 module is disabled 0 = pga2 module is enabled bit 9 abgmd: band gap reference voltage disable bit 1 = band gap reference voltage is disabled 0 = band gap reference voltage is enabled bit 8-2 unimplemented: read as 0 bit 1 ccsmd: constant-current source module disable bit 1 = constant-current source module is disabled 0 = constant-current source module is enabled bit 0 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 124 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 125 dspic33epxxgs50x family 10.0 i/o ports many of the device pins are shared among the peripher- als and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 10.1 parallel i/o (pio) ports generally, a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripherals output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents loop through, in which a ports digital output can drive the input of a peripheral that shares the same pin. figure 10-1 illus- trates how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have eight registers directly associated with their operation as digital i/os. the data direction register (trisx) determines whether the pin is an input or an out- put. if the data direction bit is a 1 , then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx), read the latch. writes to the latch, write the latch. reads from the port (portx), read the port pins, while writes to the port pins, write the latch. any bit and its associated data and control registers that are not valid for a particular device are disabled. this means the corresponding latx and trisx registers, and the port pin are read as zeros. when a pin is shared with another peripheral or func- tion that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. figure 10-1: block diag ram of a typical shared port structure note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to i/o ports (ds70000598) in the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. q d ck wr latx + trisx latch i/o pin wr portx data bus q d ck data latch read portx read trisx wr trisx peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read latx 10 1 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 126 ? 2013-2015 microchip technology inc. 10.1.1 open-drain configuration in addition to the portx, latx and trisx registers for data control, port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control x register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of out- puts other than v dd by using external pull-up resistors. the maximum open-drain voltage allowed on any pin is the same as the maximum v ih specification for that particular pin. see the pin diagrams section for the available 5v tolerant pins and tab le 2 6- 11 for the maximum v ih specification for each pin. 10.2 configuring analog and digital port pins the anselx register controls the operation of the analog port pins. the port pins that are to function as analog inputs or outputs must have their corresponding anselx and trisx bits set. in order to use port pins for i/o functionality with digital modules, such as timers, uarts, etc., the corresponding anselx bit must be cleared. the anselx register has a default value of 0xffff; therefore, all pins that share analog functions are analog (not digital) by default. pins with analog functions affected by the anselx registers are listed with a buffer type of analog in the pinout i/o descriptions (see table 1-1 ). if the trisx bit is cleared (output) while the anselx bit is set, the digital output level (v oh or v ol ) is converted by an analog peripheral, such as the adc module or comparator module. when the portx register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin, defined as a digital input (including the anx pins), can cause the input buffer to consume current that exceeds the device specifications. 10.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically, this instruction would be a nop , as shown in example 10-1 . 10.3 input change notification (icn) the input change notification function of the i/o ports allows devices to generate interrupt requests to the processor in response to a change-of-state (cos) on selected input pins. this feature can detect input change-of-states, even in sleep mode, when the clocks are disabled. every i/o port pin can be selected (enabled) for generating an interrupt request on a change-of-state. three control registers are associated with the icn functionality of each i/o port. the cnenx registers contain the icn interrupt enable control bits for each of the input pins. setting any of these bits enables an icn interrupt for the corresponding pins. each i/o pin also has a weak pull-up and a weak pull-down connected to it. the pull-ups and pull- downs act as a current source, or sink source, connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. the pull-ups and pull-downs are enabled separately, using the cnpux and the cnpdx registers, which contain the control bits for each of the pins. setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. example 10-1: port write/read example note: pull-ups and pull-downs on input change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> ; as inputs mov w0, trisb ; and portb<7:0> ; as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 127 dspic33epxxgs50x family 10.4 peripheral pin select (pps) a major challenge in general purpose devices is providing the largest possible set of peripheral features, while minimizing the conflict of features on i/o pins. the challenge is even greater on low pin count devices. in an application where more than one peripheral needs to be assigned to a single pin, inconvenient work arounds in application code, or a complete redesign, may be the only option. peripheral pin select configuration provides an alter- native to these choices by enabling peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particu- lar device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. users may independently map the input and/or output of most digital peripherals to any one of these i/o pins. hard- ware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 10.4.1 available pins the number of available pins is dependent on the par- ticular device and its pin count. pins that support the peripheral pin select feature include the label, rpn, in their full pin designation, where n is the remappable pin number. rp is used to designate pins that support both remappable input and output functions. 10.4.2 available peripherals the peripherals managed by the peripheral pin select are all digital only peripherals. these include general serial communications (uart and spi), general pur- pose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs. in comparison, some digital only peripheral modules are never included in the peripheral pin select feature. this is because the peripherals function requires special i/o circuitry on a specific port and cannot be easily connected to multiple pins. one example includes i 2 c modules. a similar requirement excludes all modules with analog inputs, such as the adc converter. a key difference between remappable and non- remappable peripherals is that remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. 10.4.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of sfrs: one to map peripheral inputs and one to map outputs. because they are separately con- trolled, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral- selectable pin is handled in two different ways, depending on whether an input or output is being mapped. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 128 ? 2013-2015 microchip technology inc. 10.4.4 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. that is, a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 10-1 through register 10-19 ). each register contains sets of 8-bit fields, with each set associated with one of the remappable peripherals. programming a given periph- erals bit field with an appropriate 8-bit value maps the rpn pin with the corresponding value to that peripheral. for any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. for example, figure 10-2 illustrates remappable pin selection for the u1rx input. figure 10-2: remappable input for u1rx 10.4.4.1 virtual connections the dspic33epxxgs50x devices support six virtual rpn pins (rp176-rp181), which are identical in functionality to all other rpn pins, with the exception of pinouts. these six pins are internal to the devices and are not connected to a physical device pin. these pins provide a simple way for inter-peripheral connection without utilizing a physical pin. for example, the output of the analog comparator can be connected to rp176 and the pwm fault input can be configured for rp176 as well. this configuration allows the analog comparator to trigger pwm faults without the use of an actual physical pin on the device. rp0 rp1 rp2 0 12 u1rx input u1rxr<7:0> to peripheral rpn n note: for input only, peripheral pin select func- tionality does not have priority over trisx settings. therefore, when configuring an rpn pin for input, the corresponding bit in the trisx register must also be configured for input (set to 1 ). downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 129 dspic33epxxgs50x family table 10-1: selectable input sources (maps input to function) input name ( 1 ) function name register configuration bits external interrupt 1 int1 rpinr0 int1r<7:0> external interrupt 2 int2 rpinr1 int2r<7:0> timer1 external clock t1ck rpinr2 t1ckr<7:0> timer2 external clock t2ck rpinr3 t2ckr<7:0> timer3 external clock t3ck rpinr3 t3ckr<7:0> input capture 1 ic1 rpinr7 ic1r<7:0> input capture 2 ic2 rpinr7 ic2r<7:0> input capture 3 ic3 rpinr8 ic3r<7:0> input capture 4 ic4 rpinr8 ic4r<7:0> output compare fault a ocfa rpinr11 ocfar<7:0> pwm fault 1 flt1 rpinr12 flt1r<7:0> pwm fault 2 flt2 rpinr12 flt2r<7:0> pwm fault 3 flt3 rpinr13 flt3r<7:0> pwm fault 4 flt4 rpinr13 flt4r<7:0> uart1 receive u1rx rpinr18 u1rxr<7:0> uart1 clear-to-send u1cts rpinr18 u1ctsr<7:0> uart2 receive u2rx rpinr19 u2rxr<7:0> uart2 clear-to-send u2cts rpinr19 u2ctsr<7:0> spi1 data input sdi1 rpinr20 sdi1r<7:0> spi1 clock input sck1 rpinr20 sck1r<7:0> spi1 slave select ss 1 rpinr21 ss1r<7:0> spi2 data input sdi2 rpinr22 sdi2r<7:0> spi2 clock input sck2 rpinr22 sck2r<7:0> spi2 slave select ss2 rpinr23 ss2r<7:0> pwm synch input 1 synci1 rpinr37 synci1r<7:0> pwm synch input 2 synci2 rpinr38 synci2r<7:0> pwm fault 5 flt5 rpinr42 flt5r<7:0> pwm fault 6 flt6 rpinr42 flt6r<7:0> pwm fault 7 flt7 rpinr43 flt7r<7:0> pwm fault 8 flt8 rpinr43 flt8r<7:0> note 1: unless otherwise noted, all inputs use the schmitt trigger input buffers. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 130 ? 2013-2015 microchip technology inc. 10.4.5 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. each register contains sets of 6-bit fields, with each set associated with one rpn pin (see register 10-20 through register 10-38 ). the value of the bit field cor- responds to one of the peripherals and that peripherals output is mapped to the pin (see table 10-2 and figure 10-3 ). a null output is associated with the output register reset value of 0 . this is done to ensure that remap- pable outputs remain disconnected from all output pins by default. figure 10-3: multiplexing remappable outputs for rpn 10.4.5.1 mapping limitations the control schema of the peripheral select pins is not limited to a small range of fixed peripheral configura- tions. there are no mutual or hardware-enforced lockouts between any of the peripheral mapping sfrs. literally any combination of peripheral mappings, across any or all of the rpn pins, is possible. this includes both many-to-one and one-to-many mappings of peripheral inputs, and outputs to pins. while such mappings may be technically possible from a configu- ration point of view, they may not be supportable from an electrical point of view. rpnr<5:0> 054 1 default u1tx output sdo2 output 2 pwm5l output 53 pwm5h output output data rpn downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 131 dspic33epxxgs50x family table 10-2: output selection for remappable pins (rpn) function rpnr<5:0> output name default port 000000 rpn tied to default pin u1tx 000001 rpn tied to uart1 transmit u1rts 000010 rpn tied to uart1 request-to-send u2tx 000011 rpn tied to uart2 transmit u2rts 000100 rpn tied to uart2 request-to-send sdo1 000101 rpn tied to spi1 data output sck1 000110 rpn tied to spi1 clock output ss1 000111 rpn tied to spi1 slave select sdo2 001000 rpn tied to spi2 data output sck2 001001 rpn tied to spi2 clock output ss2 001010 rpn tied to spi2 slave select oc1 010000 rpn tied to output compare 1 output oc2 010001 rpn tied to output compare 2 output oc3 010010 rpn tied to output compare 3 output oc4 010011 rpn tied to output compare 4 output acmp1 011000 rpn tied to analog comparator 1 output acmp2 011001 rpn tied to analog comparator 2 output acmp3 011010 rpn tied to analog comparator 3 output synco1 101101 rpn tied to pwm primary master time base sync output synco2 101110 rpn tied to pwm secondary master time base sync output refclko 110001 rpn tied to reference clock output acmp4 110010 rpn tied to analog comparator 4 output pwm4h 110011 rpn tied to pwm output pins associated with pwm generator 4 pwm4l 110100 rpn tied to pwm output pins associated with pwm generator 4 pwm5h 110101 rpn tied to pwm output pins associated with pwm generator 5 pwm5l 110110 rpn tied to pwm output pins associated with pwm generator 5 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 132 ? 2013-2015 microchip technology inc. 10.5 i/o helpful tips 1. in some cases, certain pins, as defined in table 26-11 under injection current, have inter- nal protection diodes to v dd and v ss . the term, injection current, is also referred to as clamp current. on designated pins, with sufficient exter- nal current-limiting precautions by the user, i/o pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings, with respect to the v ss and v dd supplies. note that when the user application forward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device, that is clamped internally by the v dd and v ss power rails, may affect the adc accuracy by four to six counts. 2. i/o pins that are shared with any analog input pin (i.e., anx) are always analog pins by default after any reset. consequently, configuring a pin as an analog input pin automatically disables the digital input pin buffer and any attempt to read the digital input level by reading portx or latx will always return a 0 , regardless of the digital logic level on the pin. to use a pin as a digital i/o pin on a shared anx pin, the user application needs to configure the analog pin configuration registers in the i/o ports module (i.e., anselx) by setting the appropriate bit that corresponds to that i/o port pin to a 0 . 3. most i/o pins have multiple functions. referring to the device pin diagrams in this data sheet, the prior- ities of the functions allocated to any pins are indicated by reading the pin name from left-to-right. the left most function name takes precedence over any function to its right in the naming convention. for example: an16/t2ck/t7ck/rc1; this indi- cates that an16 is the highest priority in this example and will supersede all other functions to its right in the list. those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. this rule applies to all of the functions listed for a given pin. 4. each pin has an internal weak pull-up resistor and pull-down resistor that can be configured using the cnpux and cnpdx registers, respectively. these resistors eliminate the need for external resistors in certain applications. the internal pull-up is up to ~(v dd C 0.8), not v dd . this value is still above the minimum v ih of cmos and ttl devices. 5. when driving leds directly, the i/o pin can source or sink more current than what is specified in the v oh /i oh and v ol /i ol dc characteristics specifica- tion. the respective i oh and i ol current rating only applies to maintaining the corresponding output at or above the v oh , and at or below the v ol levels. however, for leds, unlike digital inputs of an exter- nally connected device, they are not governed by the same minimum v ih /v il levels. an i/o pin output can safely sink or source any current less than that listed in the absolute maximum ratings in section 26.0 electrical characteristics of this data sheet. for example: v oh = 2.4v @ i oh = -8 ma and v dd = 3.3v the maximum output current sourced by any 8 ma i/o pin = 12 ma. led source current < 12 ma is technically permitted. refer to the v oh /i oh graphs in section 27.0 dc and ac device characteristics graphs for additional information. note: although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital i/o output function, trisx = 0x0, while the analog function is also enabled. however, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would create signal contention between the analog signal and the output pin driver. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 133 dspic33epxxgs50x family 6. the peripheral pin select (pps) pin mapping rules are as follows: a) only one output function can be active on a given pin at any time, regardless if it is a dedicated or remappable function (one pin, one output). b) it is possible to assign a remappable output function to multiple pins and externally short or tie them together for increased current drive. c) if any dedicated output function is enabled on a pin, it will take precedence over any remappable output function. d) if any dedicated digital (input or output) func- tion is enabled on a pin, any number of input remappable functions can be mapped to the same pin. e) if any dedicated analog function(s) are enabled on a given pin, digital input(s) of any kind will all be disabled, although a single dig- ital output, at the users cautionary discretion, can be enabled and active as long as there is no signal contention with an external analog input signal. for example, it is possible for the adc to convert the digital output logic level, or to toggle a digital output on a comparator or adc input, provided there is no external analog input, such as for a built-in self-test. f) any number of input remappable functions can be mapped to the same pin(s) at the same time, including to any pin with a single output from either a dedicated or remappable output. g) the trisx registers control only the digital i/o output buffer. any other dedicated or remap- pable active output will automatically override the trisx setting. the trisx register does not control the digital logic input buffer. remap- pable digital inputs do not automatically override trisx settings, which means that the trisx bit must be set to input for pins with only remappable input function(s) assigned. h) all analog pins are enabled by default after any reset and the corresponding digital input buffer on the pin has been disabled. only the analog pin select x (anselx) registers control the dig- ital input buffer, not the trisx register. the user must disable the analog function on a pin using the analog pin select x registers in order to use any digital input(s) on a corresponding pin, no exceptions. 10.6 i/o ports resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 10.6.1 key resources i/o ports (ds70000598) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 134 ? 2013-2015 microchip technology inc. 10.7 peripheral pin select registers register 10-1: rpinr0: peripheral pin select input register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int1r<7:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 int1r<7:0>: assign external interrupt 1 (int1) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 unimplemented: read as 0 register 10-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2r<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 int2r<7:0>: assign external interrupt 2 (int2) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 135 dspic33epxxgs50x family register 10-3: rpinr2: peripheral pin select input register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckr<7:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 t1ckr<7:0>: assign timer1 external clock (t1ck) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 136 ? 2013-2015 microchip technology inc. register 10-4: rpinr3: peripheral pin select input register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t3ckr7 t3ckr6 t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ckr7 t2ckr6 t2ckr5 t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 t3ckr<7:0>: assign timer3 external clock (t3ck) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 0000001 = input tied to rp1 0000000 = input tied to v ss bit 7-0 t2ckr<7:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 137 dspic33epxxgs50x family register 10-5: rpinr7: peripheral pin select input register 7 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic2r7 ic2r6 ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic1r7 ic1r6 ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 ic2r<7:0>: assign input capture 2 (ic2) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 ic1r<7:0>: assign input capture 1 (ic1) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 138 ? 2013-2015 microchip technology inc. register 10-6: rpinr8: peripheral pin select input register 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic4r7 ic4r6 ic4r5 ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic3r7 ic3r6 ic3r5 ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 ic4r<7:0>: assign input capture 4 (ic4) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 ic3r<7:0>: assign input capture 3 (ic3) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 139 dspic33epxxgs50x family register 10-7: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocfar<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 ocfar<7:0>: assign output compare fault a (ocfa) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 140 ? 2013-2015 microchip technology inc. register 10-8: rpinr12: peripheral pin select input register 12 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt2r7 flt2r6 flt2r5 flt2r4 flt2r3 flt2r2 flt2r1 flt2r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt1r7 flt1r6 flt1r5 flt1r4 flt1r3 flt1r2 flt1r1 flt1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 flt2r<7:0>: assign pwm fault 2 (flt2) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 flt1r<7:0>: assign pwm fault 1 (flt1) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 141 dspic33epxxgs50x family register 10-9: rpinr13: peripheral pin select input register 13 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt4r7 flt4r6 flt4r5 flt4r4 flt4r3 flt4r2 flt4r1 flt4r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt3r7 flt3r6 flt3r5 flt3r4 flt3r3 flt3r2 flt3r1 flt3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 flt4r<7:0>: assign pwm fault 4 (flt4) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 flt3r<7:0>: assign pwm fault 3 (flt3) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 142 ? 2013-2015 microchip technology inc. register 10-10: rpinr18: peripheral pin select input register 18 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u1ctsr7 u1ctsr6 u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u1rxr7 u1rxr6 u1rxr5 u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 u1ctsr<7:0>: assign uart1 clear-to-send (u1 cts ) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 u1rxr<7:0>: assign uart1 receive (u1rx) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 143 dspic33epxxgs50x family register 10-11: rpinr19: peripheral pin select input register 19 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u2ctsr7 u2ctsr6 u2ctsr5 u2ctsr4 u2ctsr3 u2ctsr2 u2ctsr1 u2ctsr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u2rxr7 u2rxr6 u2rxr5 u2rxr4 u2rxr3 u2rxr2 u2rxr1 u2rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 u2ctsr<7:0>: assign uart2 clear-to-send (u2cts ) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 u2rxr<7:0>: assign uart2 receive (u2rx) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 144 ? 2013-2015 microchip technology inc. register 10-12: rpinr20: peripheral pin select input register 20 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sck1inr7 sck1inr6 sck1inr5 sck1inr4 sck1inr3 sck1inr2 sck1inr1 sck1inr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdi1r7 sdi1r6 sdi1r5 sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 sck1inr<7:0>: assign spi1 clock input (sck1) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 sdi1r<7:0>: assign spi1 data input (sdi1) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 145 dspic33epxxgs50x family register 10-13: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ss1r<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 ss1r<7:0>: assign spi1 slave select (ss 1 ) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 146 ? 2013-2015 microchip technology inc. register 10-14: rpinr22: peripheral pin select input register 22 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sck2inr7 sck2inr6 sck2inr5 sck2inr4 sck2inr3 sck2inr2 sck2inr1 sck2inr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdi2r7 sdi2r6 sdi2r5 sdi2r4 sdi2r3 sdi2r2 sdi2r1 sdi2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 sck2inr<7:0>: assign spi2 clock input (sck2) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 sdi2r<7:0>: assign spi2 data input (sdi2) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 147 dspic33epxxgs50x family register 10-15: rpinr23: peripheral pin select input register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ss2r<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 ss2r<7:0>: assign spi2 slave select (ss2 ) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 148 ? 2013-2015 microchip technology inc. register 10-16: rpinr37: peripheral pin select input register 37 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 synci1r<7:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 synci1r<7:0>: assign pwm synchronization input 1 to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 149 dspic33epxxgs50x family register 10-17: rpinr38: peripheral pin select input register 38 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 synci2r<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 synci2r<7:0>: assign pwm synchronization input 2 to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 150 ? 2013-2015 microchip technology inc. register 10-18: rpinr42: peripheral pin select input register 42 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt6r7 flt6r6 flt6r5 flt6r4 flt6r3 flt6r2 flt6r1 flt6r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt5r7 flt5r6 flt5r5 flt5r4 flt5r3 flt5r2 flt5r1 flt5r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 flt6r<7:0>: assign pwm fault 6 (flt6) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 flt5r<7:0>: assign pwm fault 5 (flt5) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 151 dspic33epxxgs50x family register 10-19: rpinr43: peripheral pin select input register 43 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt8r7 flt8r6 flt8r5 flt8r4 flt8r3 flt8r2 flt8r1 flt8r0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flt7r7 flt7r6 flt7r5 flt7r4 flt7r3 flt7r2 flt7r1 flt7r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 flt8r<7:0>: assign pwm fault 8 (flt8) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss bit 7-0 flt7r<7:0>: assign pwm fault 7 (flt7) to the corresponding rpn pin bits 10110101 = input tied to rp181 10110100 = input tied to rp180 00000001 = input tied to rp1 00000000 = input tied to v ss downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 152 ? 2013-2015 microchip technology inc. register 10-20: rpor0: peripheral pin select output register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp33r5 rp33r4 rp33r3 rp33r2 rp33r1 rp33r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp32r5 rp32r4 rp32r3 rp32r2 rp32r1 rp32r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp33r<5:0>: peripheral output function is assigned to rp33 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp32r<5:0>: peripheral output function is assigned to rp32 output pin bits (see table 10-2 for peripheral function numbers) register 10-21: rpor1: peripheral pin select output register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp35r5 rp35r4 rp35r3 rp35r2 rp35r1 rp35r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp34r5 rp34r4 rp34r3 rp34r2 rp34r1 rp34r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp35r<5:0>: peripheral output function is assigned to rp35 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp34r<5:0>: peripheral output function is assigned to rp34 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 153 dspic33epxxgs50x family register 10-22: rpor2: peripheral pin select output register 2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp37r5 rp37r4 rp37r3 rp37r2 rp37r1 rp37r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp36r5 rp36r4 rp36r3 rp36r2 rp36r1 rp36r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp37r<5:0>: peripheral output function is assigned to rp37 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp36r<5:0>: peripheral output function is assigned to rp36 output pin bits (see table 10-2 for peripheral function numbers) register 10-23: rpor3: peripheral pin select output register 3 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp39r5 rp39r4 rp39r3 rp39r2 rp39r1 rp39r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp38r5 rp38r4 rp38r3 rp38r2 rp38r1 rp38r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp39r<5:0>: peripheral output function is assigned to rp39 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp38r<5:0>: peripheral output function is assigned to rp38 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 154 ? 2013-2015 microchip technology inc. register 10-24: rpor4: peripheral pin select output register 4 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp41r5 rp41r4 rp41r3 rp41r2 rp41r1 rp41r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp40r5 rp40r4 rp40r3 rp40r2 rp40r1 rp40r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp41r<5:0>: peripheral output function is assigned to rp41 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp40r<5:0>: peripheral output function is assigned to rp40 output pin bits (see table 10-2 for peripheral function numbers) register 10-25: rpor5: peripheral pin select output register 5 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp43r5 rp43r4 rp43r3 rp43r2 rp43r1 rp43r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp42r5 rp42r4 rp42r3 rp42r2 rp42r1 rp42r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp43r<5:0>: peripheral output function is assigned to rp43 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp42r<5:0>: peripheral output function is assigned to rp42 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 155 dspic33epxxgs50x family register 10-26: rpor6: peripheral pin select output register 6 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp45r5 rp45r4 rp45r3 rp45r2 rp45r1 rp45r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp44r5 rp44r4 rp44r3 rp44r2 rp44r1 rp44r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp45r<5:0>: peripheral output function is assigned to rp45 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp44r<5:0>: peripheral output function is assigned to rp44 output pin bits (see table 10-2 for peripheral function numbers) register 10-27: rpor7: peripheral pin select output register 7 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp47r5 rp47r4 rp47r3 rp47r2 rp47r1 rp47r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp46r5 rp46r4 rp46r3 rp46r2 rp46r1 rp46r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp47r<5:0>: peripheral output function is assigned to rp47 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp46r<5:0>: peripheral output function is assigned to rp46 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 156 ? 2013-2015 microchip technology inc. register 10-28: rpor8: peripheral pin select output register 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp49r5 rp49r4 rp49r3 rp49r2 rp49r1 rp49r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp48r5 rp48r4 rp48r3 rp48r2 rp48r1 rp48r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp49r<5:0>: peripheral output function is assigned to rp49 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp48r<5:0>: peripheral output function is assigned to rp48 output pin bits (see table 10-2 for peripheral function numbers) register 10-29: rpor9: peripheral pin select output register 9 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp51r5 rp51r4 rp51r3 rp51r2 rp51r1 rp51r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp50r5 rp50r4 rp50r3 rp50r2 rp50r1 rp50r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp51r<5:0>: peripheral output function is assigned to rp51 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp50r<5:0>: peripheral output function is assigned to rp50 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 157 dspic33epxxgs50x family register 10-30: rpor10: peripheral pin select output register 10 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp53r5 rp53r4 rp53r3 rp53r2 rp53r1 rp53r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp52r5 rp52r4 rp52r3 rp52r2 rp52r1 rp52r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp53r<5:0>: peripheral output function is assigned to rp53 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp52r<5:0>: peripheral output function is assigned to rp52 output pin bits (see table 10-2 for peripheral function numbers) register 10-31: rpor11: peripheral pin select output register 11 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp55r5 rp55r4 rp55r3 rp55r2 rp55r1 rp55r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp54r5 rp54r4 rp54r3 rp54r2 rp54r1 rp54r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp55r<5:0>: peripheral output function is assigned to rp55 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp54r<5:0>: peripheral output function is assigned to rp54 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 158 ? 2013-2015 microchip technology inc. register 10-32: rpor12: peripheral pin select output register 12 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp57r5 rp57r4 rp57r3 rp57r2 rp57r1 rp57r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp56r5 rp56r4 rp56r3 rp56r2 rp56r1 rp56r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp57r<5:0>: peripheral output function is assigned to rp57 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp56r<5:0>: peripheral output function is assigned to rp56 output pin bits (see table 10-2 for peripheral function numbers) register 10-33: rpor13: peripheral pin select output register 13 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp59r5 rp59r4 rp59r3 rp59r2 rp59r1 rp59r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp58r5 rp58r4 rp58r3 rp58r2 rp58r1 rp58r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp59r<5:0>: peripheral output function is assigned to rp59 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp58r<5:0>: peripheral output function is assigned to rp58 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 159 dspic33epxxgs50x family register 10-34: rpor14: peripheral pin select output register 14 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp61r5 rp61r4 rp61r3 rp61r2 rp61r1 rp61r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp60r5 rp60r4 rp60r3 rp60r2 rp60r1 rp60r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp61r<5:0>: peripheral output function is assigned to rp61 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp60r<5:0>: peripheral output function is assigned to rp60 output pin bits (see table 10-2 for peripheral function numbers) register 10-35: rpor15: peripheral pin select output register 15 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp63r5 rp63r4 rp63r3 rp63r2 rp63r1 rp63r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp62r5 rp62r4 rp62r3 rp62r2 rp62r1 rp62r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp63r<5:0>: peripheral output function is assigned to rp63 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp62r<5:0>: peripheral output function is assigned to rp62 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 160 ? 2013-2015 microchip technology inc. register 10-36: rpor16: peripheral pin select output register 16 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp177r5 rp177r4 rp177r3 rp177r2 rp177r1 rp177r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp176r5 rp176r4 rp176r3 rp176r2 rp176r1 rp176r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp177r<5:0>: peripheral output function is assigned to rp177 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp176r<5:0>: peripheral output function is assigned to rp176 output pin bits (see table 10-2 for peripheral function numbers) register 10-37: rpor17: peripheral pin select output register 17 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp179r5 rp179r4 rp179r3 rp179r2 rp179r1 rp179r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp178r5 rp178r4 rp178r3 rp178r2 rp178r1 rp178r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp179r<5:0>: peripheral output function is assigned to rp179 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp178r<5:0>: peripheral output function is assigned to rp178 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 161 dspic33epxxgs50x family register 10-38: rpor18: peripheral pin select output register 18 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp181r5 rp181r4 rp181r3 rp181r2 rp181r1 rp181r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp180r5 rp180r4 rp180r3 rp180r2 rp180r1 rp180r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 rp181r<5:0>: peripheral output function is assigned to rp181 output pin bits (see table 10-2 for peripheral function numbers) bit 7-6 unimplemented: read as 0 bit 5-0 rp180r<5:0>: peripheral output function is assigned to rp180 output pin bits (see table 10-2 for peripheral function numbers) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 162 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 163 dspic33epxxgs50x family 11.0 timer1 the timer1 module is a 16-bit timer that can operate as a free-running interval timer/counter. the timer1 module has the following unique features over other timers: can be operated in asynchronous counter mode from an external clock source the external clock input (t1ck) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler a block diagram of timer1 is shown in figure 11-1 . the timer1 module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode asynchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous and asynchronous counter modes, the input clock is derived from the external clock input at the t1ck pin. the timer modes are determined by the following bits: timer clock source control bit (tcs): t1con<1> timer synchronization control bit (tsync): t1con<2> timer gate control bit (tgate): t1con<6> timer control bit settings for different operating modes are provided in table 11-1 . table 11-1: timer mode settings figure 11-1: 16-bit time r1 module block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to timers (ds70362) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. mode tcs tgate tsync timer 00x gated timer 01x synchronous counter 1x1 asynchronous counter 1x0 tgate tcs 00 10x1 pr1 tgate set t1if flag 0 1 tsync 1 0 sync equal reset t1ck prescaler (/n) tckps<1:0> gate sync f p (1) falling edge detect tckps<1:0> note 1: f p is the peripheral clock. latch data clk t1clk adc trigger tmr1 comparator prescaler (/n) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 164 ? 2013-2015 microchip technology inc. 11.1 timer1 resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 11.1.1 key resources timers (ds70362) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 165 dspic33epxxgs50x family 11.2 timer1 control register register 11-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 1 ) t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate tckps1 tckps0 tsync ( 1 ) tcs ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit ( 1 ) 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as 0 bit 13 tsidl: timer1 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as 0 bit 2 tsync: timer1 external clock input synchronization select bit ( 1 ) when tcs = 1 : 1 = synchronizes external clock input 0 = does not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit ( 1 ) 1 = external clock is from pin, t1ck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as 0 note 1: when timer1 is enabled in external synchronous counter mode (tcs = 1 , tsync = 1 , ton = 1 ), any attempts by user software to write to the tmr1 register are ignored. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 166 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 167 dspic33epxxgs50x family 12.0 timer2/3 and timer4/5 the timer2/3 and timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. as 32-bit timers, timer2/3 and timer4/5 operate in three modes: two independent 16-bit timers (e.g., timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) single 32-bit timer single 32-bit synchronous counter they also support these features: timer gate operation selectable prescaler settings timer operation during idle and sleep modes interrupt on a 32-bit period register match time base for input capture and output compare modules (timer2 and timer3 only) individually, all four of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed previously, except for the event trigger; this is implemented only with timer2/3. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con and t5con registers. t2con and t4con are shown in generic form in register 12-1 . t3con and t5con are shown in register 12-2 . for 32-bit timer/counter operation, timer2 and timer4 are the least significant word (lsw); timer3 and timer5 are the most significant word (msw) of the 32-bit timers. a block diagram for an example 32-bit timer pair (timer2/3 and timer4/5) is shown in figure 12-2 . 12.1 timer resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 12.1.1 key resources timers (ds70362) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to timers (ds70362) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: for 32-bit operation, t3con and t5con control bits are ignored. only t2con and t4con control bits are used for setup and control. timer2 and timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the timer3 and timer5 interrupt flags. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 168 ? 2013-2015 microchip technology inc. figure 12-1: timerx block diagram (x = 2 through 5) figure 12-2: type b/type c timer pair block diagram (32-bit timer) note 1: f p is the peripheral clock. 2: the adc trigger is only available on tmr2. tgate tcs 00 10x1 prx tgate set txif flag 0 1 equal reset txck tckps<1:0> gate sync f p (1) falling edge detect tckps<1:0> latch data clk txclk tmrx comparator prescaler (/n) prescaler (/n) sync adc trigger (2) tgate tcs 00 10x1 comparator tgate set tyif flag 0 1 equal reset txck tckps<1:0> f p (1) tckps<1:0> note 1: timerx is a type b timer (x = 2 and 4). 2: timery is a type c timer (y = 3 and 5). data clk prx tmryhld data bus<15:0> msw lsw prescaler (/n) prescaler (/n) sync gate sync falling edge detect pry tmrx tmry latch downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 169 dspic33epxxgs50x family 12.2 timer control registers register 12-1: txcon: (timer2 and timer4) control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate tckps1 tckps0 t32 t c s ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when t32 = 1 : 1 = starts 32-bit timerx/y 0 = stops 32-bit timerx/y when t32 = 0 : 1 = starts 16-bit timerx 0 = stops 16-bit timerx bit 14 unimplemented: read as 0 bit 13 tsidl: timerx stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit 1 = timerx and timery form a single 32-bit timer 0 = timerx and timery act as two 16-bit timers bit 2 unimplemented: read as 0 bit 1 tcs: timerx clock source select bit ( 1 ) 1 = external clock is from pin, txck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as 0 note 1: the txck pin is not available on all devices. refer to the pin diagrams section for the available pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 170 ? 2013-2015 microchip technology inc. register 12-2: tycon: (timer 3 and timer5) control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 1 ) t s i d l ( 2 ) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 t g a t e ( 1 ) tckps1 ( 1 ) tckps0 ( 1 ) t c s ( 1 , 3 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timery on bit ( 1 ) 1 = starts 16-bit timery 0 = stops 16-bit timery bit 14 unimplemented: read as 0 bit 13 tsidl: timery stop in idle mode bit ( 2 ) 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timery gated time accumulation enable bit ( 1 ) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timery input clock prescale select bits ( 1 ) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as 0 bit 1 tcs: timery clock source select bit ( 1 , 3 ) 1 = external clock is from pin, tyck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as 0 note 1: when 32-bit operation is enabled (txcon<3> = 1 ), these bits have no effect on timery operation; all timer functions are set through txcon. 2: when 32-bit timer operation is enabled (t32 = 1 ) in the timerx control register (txcon<3>), the tsidl bit must be cleared to operate the 32-bit timer in idle mode. 3: the tyck pin is not available on all devices. see the pin diagrams section for the available pins. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 171 dspic33epxxgs50x family 13.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurements. the dspic33epxxgs50x family devices support four input capture channels. key features of the input capture module include: hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules synchronous and trigger modes of output compare operation, with up to 21 user-selectable trigger/sync sources available a 4-level fifo buffer for capturing and holding timer values for several events configurable interrupt generation up to six clock sources available for each module, driving a separate internal 16-bit counter 13.1 input capture resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 13.1.1 key resources input capture (ds70000352) in the dspic33/ pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools figure 13-1: input capture x module block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to input capture (ds70000352) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. icxbuf 4-level fifo buffer icx pin icm<2:0> set icxif edge detect logic ici<1:0> icov, icbne interrupt logic system bus prescaler counter 1:1/4/16 and clock synchronizer event and trigger and sync logic clock select icx clock sources trigger and sync sources ictsel<2:0> 16 16 16 icxtmr increment reset note 1: the trigger/sync source is enabled by default and is set to timer3 as a source. this timer must be enabled for proper icx module operation or the trigger/sync source must be changed to another source option. syncsel<4:0> (1) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 172 ? 2013-2015 microchip technology inc. 13.2 input capture registers register 13-1: icxcon1: input capture x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 icsidl ictsel2 ictsel1 ictsel0 bit 15 bit 8 u-0 r/w-0 r/w-0 r-0, hc, hs r-0, hc, hs r/w-0 r/w-0 r/w-0 ici1 ici0 icov icbne icm2 icm1 icm0 bit 7 bit 0 legend: hc = hardware clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 icsidl: input capture x stop in idle control bit 1 = input capture will halt in cpu idle mode 0 = input capture will continue to operate in cpu idle mode bit 12-10 ictsel<2:0>: input capture x timer select bits 111 = peripheral clock (f p ) is the clock source of the icx 110 = reserved 101 = reserved 100 = t1clk is the clock source of the icx (only the synchronous clock is supported) 011 = t5clk is the clock source of the icx 010 = t4clk is the clock source of the icx 001 = t2clk is the clock source of the icx 000 = t3clk is the clock source of the icx bit 9-7 unimplemented: read as 0 bit 6-5 ici<1:0>: number of captures per interrupt select bits (this field is not used if icm<2:0> = 001 or 111 ) 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture x overflow status flag bit (read-only) 1 = input capture buffer overflow has occurred 0 = no input capture buffer overflow has occurred bit 3 icbne: input capture x buffer not empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture x mode select bits 111 = input capture x functions as an interrupt pin only in cpu sleep and idle modes (rising edge detect only, all other control bits are not applicable) 110 = unused (module is disabled) 101 = capture mode, every 16th rising edge (prescaler capture mode) 100 = capture mode, every 4th rising edge (prescaler capture mode) 011 = capture mode, every rising edge (simple capture mode) 010 = capture mode, every falling edge (simple capture mode) 001 = capture mode, every rising and falling edge (edge detect mode, ici<1:0>, is not used in this mode) 000 = input capture x is turned off downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 173 dspic33epxxgs50x family register 13-2: icxcon2: input capture x control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 i c 3 2 bit 15 bit 8 r/w-0 r/w-0, hs u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 ictrig ( 2 ) trigstat ( 3 ) syncsel4 ( 4 ) syncsel3 ( 4 ) syncsel2 ( 4 ) syncsel1 ( 4 ) syncsel0 ( 4 ) bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as 0 bit 8 ic32: input capture x 32-bit timer mode select bit (cascade mode) 1 = odd icx and even icx form a single 32-bit input capture module ( 1 ) 0 = cascade module operation is disabled bit 7 ictrig: input capture x trigger operation select bit ( 2 ) 1 = input source is used to trigger the input capture timer (trigger mode) 0 = input source is used to synchronize the input capture timer to a timer of another module (synchronization mode) bit 6 trigstat: timer trigger status bit ( 3 ) 1 = icxtmr has been triggered and is running 0 = icxtmr has not been triggered and is being held clear bit 5 unimplemented: read as 0 note 1: the ic32 bit in both the odd and even icx must be set to enable cascade mode. 2: the input source is selected by the syncsel<4:0> bits of the icxcon2 register. 3: this bit is set by the selected input source (selected by syncsel<4:0> bits); it can be read, set and cleared in software. 4: do not use the icx module as its own sync or trigger source. 5: this option should only be selected as a trigger source and not as a synchronization source. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 174 ? 2013-2015 microchip technology inc. bit 4-0 syncsel<4:0>: input source select for synchronization and trigger operation bits ( 4 ) 11111 = no sync or trigger source for icx 11110 = reserved 11101 = reserved 11100 = reserved 11011 = cmp4 module synchronizes or triggers icx ( 5 ) 11010 = cmp3 module synchronizes or triggers icx ( 5 ) 11001 = cmp2 module synchronizes or triggers icx ( 5 ) 11000 = cmp1 module synchronizes or triggers icx ( 5 ) 10111 = reserved 10110 = reserved 10101 = reserved 10100 = reserved 10011 = ic4 module interrupt synchronizes or triggers icx 10010 = ic3 module interrupt synchronizes or triggers icx 10001 = ic2 module interrupt synchronizes or triggers icx 10000 = ic1 module interrupt synchronizes or triggers icx 01111 = timer5 synchronizes or triggers icx 01110 = timer4 synchronizes or triggers icx 01101 = timer3 synchronizes or triggers icx (default) 01100 = timer2 synchronizes or triggers icx 01011 = timer1 synchronizes or triggers icx 01010 = reserved 01001 = reserved 01000 = ic4 module synchronizes or triggers icx 00111 = ic3 module synchronizes or triggers icx 00110 = ic2 module synchronizes or triggers icx 00101 = ic1 module synchronizes or triggers icx 00100 = oc4 module synchronizes or triggers icx 00011 = oc3 module synchronizes or triggers icx 00010 = oc2 module synchronizes or triggers icx 00001 = oc1 module synchronizes or triggers icx 00000 = no sync or trigger source for icx register 13-2: icxcon2: input capture x control register 2 (continued) note 1: the ic32 bit in both the odd and even icx must be set to enable cascade mode. 2: the input source is selected by the syncsel<4:0> bits of the icxcon2 register. 3: this bit is set by the selected input source (selected by syncsel<4:0> bits); it can be read, set and cleared in software. 4: do not use the icx module as its own sync or trigger source. 5: this option should only be selected as a trigger source and not as a synchronization source. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 175 dspic33epxxgs50x family 14.0 output compare the output compare module can select one of six available clock sources for its time base. the module compares the value of the timer with the value of one or two compare registers, depending on the operating mode selected. the state of the output pin changes when the timer value matches the compare register value. the output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. 14.1 output compare resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 14.1.1 key resources output compare with dedicated timer (ds70005159) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools figure 14-1: output compare x module block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to output compare with dedicated timer (ds70005159) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. ocxr buffer ocxcon1 ocxcon2 ocx interrupt ocx pin ocxrs buffer comparator match match trigger and sync logic clock select increment reset ocx clock sources trigger and sync sources reset match event ocfa ocxr ocxrs event event rollover rollover/reset rollover/reset ocx synchronization/trigger event syncsel<4:0> trigger (1) note 1: the trigger/sync source is enabled by default and is set to timer2 as a source. this timer must be enabled for proper ocx module operation or the trigger/sync source must be changed to another source option. ocx output and fault logic comparator ocxtmr downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 176 ? 2013-2015 microchip technology inc. 14.2 output compare control registers register 14-1: ocxcon1: output compare x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ocsidl octsel2 octsel1 octsel0 bit 15 bit 8 r/w-0 u-0 u-0 r/w-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 enflta ocflta trigmode ocm2 ocm1 ocm0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 ocsidl: output compare x stop in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-10 octsel<2:0>: output compare x clock select bits 111 = peripheral clock (f p ) 110 = reserved 101 = reserved 100 = t1clk is the clock source of the ocx (only the synchronous clock is supported) 011 = t5clk is the clock source of the ocx 010 = t4clk is the clock source of the ocx 001 = t3clk is the clock source of the ocx 000 = t2clk is the clock source of the ocx bit 9-8 unimplemented: read as 0 bit 7 enflta: fault a input enable bit 1 = output compare fault a input (ocfa) is enabled 0 = output compare fault a input (ocfa) is disabled bit 6-5 unimplemented: read as 0 bit 4 ocflta: pwm fault a condition status bit 1 = pwm fault a condition on the ocfa pin has occurred 0 = no pwm fault a condition on the ocfa pin has occurred bit 3 trigmode: trigger status mode select bit 1 = trigstat (ocxcon2<6>) is cleared when ocxrs = ocxtmr or in software 0 = trigstat is cleared only by software note 1: ocxr and ocxrs are double-buffered in pwm mode only. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 177 dspic33epxxgs50x family bit 2-0 ocm<2:0>: output compare x mode select bits 111 = center-aligned pwm mode: output is set high when ocxtmr = ocxr and set low when ocxtmr = ocxrs ( 1 ) 110 = edge-aligned pwm mode: output is set high when ocxtmr = 0 and set low when ocxtmr = ocxr ( 1 ) 101 = double compare continuous pulse mode: initializes ocx pin low, toggles ocx state continuously on alternate matches of ocxr and ocxrs 100 = double compare single-shot mode: initializes ocx pin low, toggles ocx state on matches of ocxr and ocxrs for one cycle 011 = single compare mode: compare event with ocxr, continuously toggles ocx pin 010 = single compare single-shot mode: initializes ocx pin high, compare event with ocxr, forces ocx pin low 001 = single compare single-shot mode: initializes ocx pin low, compare event with ocxr, forces ocx pin high 000 = output compare channel is disabled register 14-1: ocxcon1: output compare x control register 1 (continued) note 1: ocxr and ocxrs are double-buffered in pwm mode only. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 178 ? 2013-2015 microchip technology inc. register 14-2: ocxcon2: output compare x control register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 fltmd fltout flttrien ocinv o c 3 2 bit 15 bit 8 r/w-0 r/w-0, hs r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 fltmd: fault mode select bit 1 = fault mode is maintained until the fault source is removed; the corresponding ocflta bit is cleared in software and a new pwmx period starts 0 = fault mode is maintained until the fault source is removed and a new pwmx period starts bit 14 fltout: fault out bit 1 = pwmx output is driven high on a fault 0 = pwmx output is driven low on a fault bit 13 flttrien: fault output state select bit 1 = ocx pin is tri-stated on a fault condition 0 = ocx pin i/o state is defined by the fltout bit on a fault condition bit 12 ocinv: output compare x invert bit 1 = ocx output is inverted 0 = ocx output is not inverted bit 11-9 unimplemented: read as 0 bit 8 oc32: cascade two ocx modules enable bit (32-bit operation) 1 = cascade module operation is enabled 0 = cascade module operation is disabled bit 7 octrig: output compare x trigger/sync select bit 1 = triggers ocx from the source designated by the syncselx bits 0 = synchronizes ocx with the source designated by the syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running 0 = timer source has not been triggered and is being held clear bit 5 octris: output compare x output pin direction select bit 1 = ocx is tri-stated 0 = ocx module drives the ocx pin note 1: do not use the ocx module as its own synchronization or trigger source. 2: when the ocy module is turned off, it sends a trigger out signal. if the ocx module uses the ocy module as a trigger source, the ocy module must be unselected as a trigger source prior to disabling it. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 179 dspic33epxxgs50x family bit 4-0 syncsel<4:0>: trigger/synchronization source selection bits 11111 = ocxrs compare event is used for synchronization 11110 = int2 pin synchronizes or triggers ocx 11101 = int1 pin synchronizes or triggers ocx 11100 = reserved 11011 = cmp4 module synchronizes or triggers ocx 11010 = cmp3 module synchronizes or triggers ocx 11001 = cmp2 module synchronizes or triggers ocx 11000 = cmp1 module synchronizes or triggers ocx 10111 = reserved 10110 = reserved 10101 = reserved 10100 = reserved 10011 = ic4 input capture interrupt event synchronizes or triggers ocx 10010 = ic3 input capture interrupt event synchronizes or triggers ocx 10001 = ic2 input capture interrupt event synchronizes or triggers ocx 10000 = ic1 input capture interrupt event synchronizes or triggers ocx 01111 = timer5 synchronizes or triggers ocx 01110 = timer4 synchronizes or triggers ocx 01101 = timer3 synchronizes or triggers ocx 01100 = timer2 synchronizes or triggers ocx (default) 01011 = timer1 synchronizes or triggers ocx 01010 = reserved 01001 = reserved 01000 = ic4 input capture event synchronizes or triggers ocx 00111 = ic3 input capture event synchronizes or triggers ocx 00110 = ic2 input capture event synchronizes or triggers ocx 00101 = ic1 input capture event synchronizes or triggers ocx 00100 = oc4 module synchronizes or triggers ocx ( 1 , 2 ) 00011 = oc3 module synchronizes or triggers ocx ( 1 , 2 ) 00010 = oc2 module synchronizes or triggers ocx ( 1 , 2 ) 00001 = oc1 module synchronizes or triggers ocx ( 1 , 2 ) 00000 = no sync or trigger source for ocx register 14-2: ocxcon2: output comp are x control register 2 (continued) note 1: do not use the ocx module as its own synchronization or trigger source. 2: when the ocy module is turned off, it sends a trigger out signal. if the ocx module uses the ocy module as a trigger source, the ocy module must be unselected as a trigger source prior to disabling it. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 180 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 181 dspic33epxxgs50x family 15.0 high-speed pwm the high-speed pwm module on dspic33epxxgs50x devices supports a wide variety of pwm modes and output formats. this pwm module is ideal for power conversion applications, such as: ac/dc converters dc/dc converters power factor correction uninterruptible power supply (ups) inverters battery chargers digital lighting 15.1 features overview the high-speed pwm module incorporates the following features: five pwmx generators with two outputs per generator two master time base modules individual time base and duty cycle for each pwm output duty cycle, dead time, phase shift and a frequency resolution of 1.04 ns independent fault and current-limit inputs redundant output true independent output center-aligned pwm mode output override control chop mode (also known as gated mode) special event trigger dual trigger from pwmx to analog-to-digital converter (adc) pwmxl and pwmxh output pin swapping independent pwmx frequency, duty cycle and phase-shift changes enhanced leading-edge blanking (leb) functionality pwm capture functionality figure 15-1 conceptualizes the pwm module in a simplified block diagram. figure 15-2 illustrates how the module hardware is partitioned for each pwmx output pair for the complementary pwm mode. the pwm module contains five pwm generators. the module has up to 10 pwmx output pins: pwm1h/ pwm1l through pwm5h/pwm5l. for complementary outputs, these 10 i/o pins are grouped into high/low pairs. 15.2 feature description the pwm module is designed for applications that require: high resolution at high pwm frequencies the ability to drive standard, edge-aligned, center-aligned complementary mode and push-pull mode outputs the ability to create multiphase pwm outputs two common, medium power converter topologies are push-pull and half-bridge. these designs require the pwm output signal to be switched between alternate pins, as provided by the push-pull pwm mode. phase-shifted pwm describes the situation where each pwm generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. multiphase pwm is often used to improve dc/dc converter load transient response, and reduce the size of output filter capacitors and inductors. multiple dc/dc converters are often operated in parallel, but phase shifted in time. a single pwm output, operating at 250 khz, has a period of 4 ? s but an array of four pwm channels, staggered by 1 ? s each, yields an effective switching frequency of 1 mhz. multiphase pwm applications typically use a fixed-phase relationship. variable phase pwm is useful in zero voltage transition (zvt) power converters. here, the pwm duty cycle is always 50% and the power flow is controlled by varying the relative phase shift between the two pwm generators. note: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to high-speed pwm module (ds70000323) in the dspic33/ pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). note: duty cycle, dead time, phase shift and frequency resolution is 8.32 ns in center-aligned pwm mode. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 182 ? 2013-2015 microchip technology inc. 15.2.1 write-protected registers on dspic33epxxgs50x family devices, write protection is implemented for the ioconx and fclconx registers. the write protection feature prevents any inadvertent writes to these registers. this protection feature can be controlled by the pwmlock configuration bit (fdevopt<0>). the default state of the write protection feature is enabled (pwmlock = 1 ). the write protection feature can be disabled by configuring pwmlock = 0 . to gain write access to these locked registers, the user application must write two consecutive values (0xabcd and 0x4321) to the pwmkey register to perform the unlock operation. the write access to the ioconx or fclconx registers must be the next sfr access following the unlock process. there can be no other sfr accesses during the unlock process and subsequent write access. to write to both the ioconx and fclconx registers requires two unlock operations. the correct unlocking sequence is described in example 15-1 . example 15-1: pwm write-protec ted register unlock sequence 15.3 pwm resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 15.3.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools ; writing to fclcon1 register requires unlock sequence mov #0xabcd, w10 ; load first unlock key to w10 register mov #0x4321, w11 ; load second unlock key to w11 register mov #0x0000, w0 ; load desired value of fclcon1 register in w0 mov w10, pwmkey ; write first unlock key to pwmkey register mov w11, pwmkey ; write second unlock key to pwmkey register mov w0, fclcon1 ; write desired value to fclcon1 register ; set pwm ownership and polarity using the iocon1 register ; writing to iocon1 register requires unlock sequence mov #0xabcd, w10 ; load first unlock key to w10 register mov #0x4321, w11 ; load second unlock key to w11 register mov #0xf000, w0 ; load desired value of iocon1 register in w0 mov w10, pwmkey ; write first unlock key to pwmkey register mov w11, pwmkey ; write second unlock key to pwmkey register mov w0, iocon1 ; write desired value to iocon1 register downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 183 dspic33epxxgs50x family figure 15-1: high-speed pwm module architectural diagram cpu master time base synci1/synci1 synco1/synco2 pwm1h pwm1l pwm1 interrupt pwm2h pwm2l pwm2 interrupt pwm5h pwm5l pwm5 interrupt synchronization signal data bus adc module fault and fault, current limit synchronization signal synchronization signal primary trigger secondary trigger special event trigger current limit fault, current limit pwm3 through pwm4 primary and secondary pwm generator 5 pwm generator 2 pwm generator 1 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 184 ? 2013-2015 microchip technology inc. figure 15-2: simplified conceptual bl ock diagram of the high-speed pwm mux ptmrx pdcx pwmconx trgconx ptcon, ptcon2 ioconx dtrx pwmxl pwmxh fltx pwm1l pwm1h fclconx mdc phasex lebconx mux stmrx sdcx sphasex altdtrx pwmcapx user override logic current-limit pwmx output mode control logic logic fault and current-limit logic pwmx generator 1 fltx pwmx generator 2 C pwmx generator 5 interrupt logic adc trigger module control and timing master duty cycle register synchronization synchronization master period master period master duty cycle master duty cycle secondary pwmx synci2 synci1 synco1 sevtcmp comparator special event trigger special event postscaler ptper pmtmr primary master time base master time base counter special event compare trigger comparator clock prescaler comparator comparator comparator 16-bit data bus dead-time trigx fault override logic override logic synco2 sevtcmp comparator special event trigger special event postscaler stper smtmr secondary master time base master time base counter special event compare trigger comparator clock prescaler stcon, stcon2 comparator strigx adc trigger pwmkey auxconx pin control logic downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 185 dspic33epxxgs50x family register 15-1: ptcon: pwmx time base control register r/w-0 u-0 r/w-0 r-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 pten ptsidl sestat seien eipu ( 1 ) syncpol ( 1 ) syncoen ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 syncen ( 1 ) syncsrc2 ( 1 ) syncsrc1 ( 1 ) syncsrc0 ( 1 ) sevtps3 ( 1 ) sevtps2 ( 1 ) sevtps1 ( 1 ) sevtps0 ( 1 ) bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pten: pwmx module enable bit 1 = pwmx module is enabled 0 = pwmx module is disabled bit 14 unimplemented: read as 0 bit 13 ptsidl: pwmx time base stop in idle mode bit 1 = pwmx time base halts in cpu idle mode 0 = pwmx time base runs in cpu idle mode bit 12 sestat: special event interrupt status bit 1 = special event interrupt is pending 0 = special event interrupt is not pending bit 11 seien: special event interrupt enable bit 1 = special event interrupt is enabled 0 = special event interrupt is disabled bit 10 eipu: enable immediate period updates bit ( 1 ) 1 = active period register is updated immediately 0 = active period register updates occur on pwmx cycle boundaries bit 9 syncpol: synchronize input and output polarity bit ( 1 ) 1 = syncix/synco1 polarity is inverted (active-low) 0 = syncix/synco1 is active-high bit 8 syncoen: primary time base synchronization enable bit ( 1 ) 1 = synco1 output is enabled 0 = synco1 output is disabled bit 7 syncen: external time base synchronization enable bit ( 1 ) 1 = external synchronization of primary time base is enabled 0 = external synchronization of primary time base is disabled bit 6-4 syncsrc<2:0>: synchronous source selection bits ( 1 ) 111 = reserved 101 = reserved 100 = reserved 011 = reserved 010 = reserved 001 = synci2 000 = synci1 note 1: these bits should be changed only when pten = 0 . in addition, when using the syncix feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 186 ? 2013-2015 microchip technology inc. bit 3-0 sevtps<3:0>: pwmx special event trigger output postscaler select bits ( 1 ) 1111 = 1:16 postscaler generates a special event trigger on every sixteenth compare match event 0001 = 1:2 postscaler generates a special event trigger on every second compare match event 0000 = 1:1 postscaler generates a special event trigger on every compare match event register 15-1: ptcon: pwmx time base control register (continued) note 1: these bits should be changed only when pten = 0 . in addition, when using the syncix feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. register 15-2: ptcon2: pwmx cl ock divider select register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pclkdiv<2:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 pclkdiv<2:0>: pwmx input clock prescaler (divider) select bits ( 1 ) 111 = reserved 110 = divide-by-64, maximum pwm timing resolution 101 = divide-by-32, maximum pwm timing resolution 100 = divide-by-16, maximum pwm timing resolution 011 = divide-by-8, maximum pwm timing resolution 010 = divide-by-4, maximum pwm timing resolution 001 = divide-by-2, maximum pwm timing resolution 000 = divide-by-1, maximum pwm timing resolution (power-on default) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 187 dspic33epxxgs50x family register 15-3: ptper: pwmx primary master time base period register ( 1 , 2 ) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ptper<15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 ptper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 ptper<15:0>: primary master time base (pmtmr) period value bits note 1: the pwmx time base has a minimum value of 0x0010 and a maximum value of 0xfff8. 2: any period value that is less than 0x0028 must have the least significant 3 bits set to 0 , thus yielding a period resolution at 8.32 ns (at fastest auxiliary clock rate). register 15-4: sevtcmp: pwmx special event compare register ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp<12:5> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 sevtcmp<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 sevtcmp<12:0>: special event compare count value bits bit 2-0 unimplemented: read as 0 note 1: one lsb = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum sevtcmp resolution is 8.32 ns. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 188 ? 2013-2015 microchip technology inc. register 15-5: stcon: pw mx secondary master time base control register u-0 u-0 u-0 r-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 sestat seien eipu ( 1 ) syncpol syncoen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 syncen syncsrc2 syncsrc1 syncsrc0 sevtps3 sevtps2 sevtps1 sevtps0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 sestat: special event interrupt status bit 1 = secondary special event interrupt is pending 0 = secondary special event interrupt is not pending bit 11 seien: special event interrupt enable bit 1 = secondary special event interrupt is enabled 0 = secondary special event interrupt is disabled bit 10 eipu: enable immediate period updates bit ( 1 ) 1 = active secondary period register is updated immediately 0 = active secondary period register updates occur on pwmx cycle boundaries bit 9 syncpol: synchronize input and output polarity bit 1 = syncix/synco2 polarity is inverted (active-low) 0 = syncix/synco2 polarity is active-high bit 8 syncoen: secondary master time base synchronization enable bit 1 = synco2 output is enabled 0 = synco2 output is disabled bit 7 syncen: external secondary master time base synchronization enable bit 1 = external synchronization of secondary time base is enabled 0 = external synchronization of secondary time base is disabled bit 6-4 syncsrc<2:0>: secondary time base sync source selection bits 111 = reserved 101 = reserved 100 = reserved 011 = reserved 010 = reserved 001 = synci2 000 = synci1 bit 3-0 sevtps<3:0>: pwmx secondary special event trigger output postscaler select bits 1111 = 1:16 postcale 0001 = 1:2 postcale 0000 = 1:1 postscale note 1: this bit only applies to the secondary master time base period. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 189 dspic33epxxgs50x family register 15-6: stcon2: pwmx secondary clock divider select register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pclkdiv<2:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 pclkdiv<2:0>: pwmx input clock prescaler (divider) select bits ( 1 ) 111 = reserved 110 = divide-by-64, maximum pwm timing resolution 101 = divide-by-32, maximum pwm timing resolution 100 = divide-by-16, maximum pwm timing resolution 011 = divide-by-8, maximum pwm timing resolution 010 = divide-by-4, maximum pwm timing resolution 001 = divide-by-2, maximum pwm timing resolution 000 = divide-by-1, maximum pwm timing resolution (power-on default) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. register 15-7: stper: pwmx secondary master time base period register ( 1 , 2 ) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 stper<15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 stper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 stper<15:0>: secondary master time base (smtmr) period value bits note 1: the pwmx time base has a minimum value of 0x0010 and a maximum value of 0xfff8. 2: any period value that is less than 0x0028 must have the least significant 3 bits set to 0 , thus yielding a period resolution at 8.32 ns (at fastest auxiliary clock rate). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 190 ? 2013-2015 microchip technology inc. register 15-8: ssevtcmp: pwmx seco ndary special event compare register ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssevtcmp<12:5> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ssevtcmp<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 ssevtcmp<12:0>: special event compare count value bits bit 2-0 unimplemented: read as 0 note 1: one lsb = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum sevtcmp resolution is 8.32 ns. register 15-9: chop: pwmx ch op clock generator register ( 1 ) r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 chpclken chopclk6 chopclk5 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 chopclk4 chopclk3 chopclk2 chopclk1 chopclk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 chpclken: enable chop clock generator bit 1 = chop clock generator is enabled 0 = chop clock generator is disabled bit 14-10 unimplemented: read as 0 bit 9-3 chopclk<6:0>: chop clock divider bits value is in 8.32 ns increments. the frequency of the chop clock signal is given by: chop frequency = 1/(16.64 * (chop<7:3> + 1) * primary master pwm input clock period) bit 2-0 unimplemented: read as 0 note 1: the chop clock generator operates with the primary pwmx clock prescaler (pclkdiv<2:0>) in the ptcon2 register ( register 15-2 ). downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 191 dspic33epxxgs50x family register 15-10: mdc: pwmx master duty cycle register ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 mdc<15:0>: pwmx master duty cycle value bits note 1: the smallest pulse width that can be generated on the pwmx output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of period C 0x0008. 2: as the duty cycle gets closer to 0% or 100% of the pwmx period (0 to 40 ns, depending on the mode of operation), pwmx duty cycle resolution will increase from 1 to 3 lsbs. register 15-11: pwmkey: pwmx protection lock/unlock key register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmkey<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 pwmkey<15:0>: pwmx protection lock/unlock key value bits downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 192 ? 2013-2015 microchip technology inc. register 15-12: pwmconx: pwmx co ntrol register (x = 1 to 5) r-0, hsc r-0, hsc r-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltstat ( 1 ) clstat ( 1 ) trgstat fltien clien trgien itb ( 3 ) mdcs ( 3 ) bit 15 bit 8 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 dtc1 dtc0 m t b sc a m ( 2 , 3 , 4 ) xpres ( 5 ) iue bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 fltstat: fault interrupt status bit ( 1 ) 1 = fault interrupt is pending 0 = no fault interrupt is pending this bit is cleared by setting fltien = 0 . bit 14 clstat: current-limit interrupt status bit ( 1 ) 1 = current-limit interrupt is pending 0 = no current-limit interrupt is pending this bit is cleared by setting clien = 0 . bit 13 trgstat: trigger interrupt status bit 1 = trigger interrupt is pending 0 = no trigger interrupt is pending this bit is cleared by setting trgien = 0 . bit 12 fltien: fault interrupt enable bit 1 = fault interrupt is enabled 0 = fault interrupt is disabled and the fltstat bit is cleared bit 11 clien: current-limit interrupt enable bit 1 = current-limit interrupt is enabled 0 = current-limit interrupt is disabled and the clstat bit is cleared bit 10 trgien: trigger interrupt enable bit 1 = a trigger event generates an interrupt request 0 = trigger event interrupts are disabled and the trgstat bit is cleared bit 9 itb: independent time base mode bit ( 3 ) 1 = phasex/sphasex registers provide the time base period for this pwmx generator 0 = ptper register provides timing for this pwmx generator bit 8 mdcs: master duty cycle register select bit ( 3 ) 1 = mdc register provides duty cycle information for this pwmx generator 0 = pdcx and sdcx registers provide duty cycle information for this pwmx generator note 1: software must clear the interrupt status here and in the corresponding ifsx bit in the interrupt controller. 2: the independent time base mode (itb = 1 ) must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 3: these bits should not be changed after the pwmx is enabled by setting pten = 1 (ptcon<15>). 4: center-aligned mode ignores the least significant 3 bits of the duty cycle, phase and dead-time registers. the highest center-aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest clock. 5: configure clmod = 0 (fclconx<8>) and itb = 1 (pwmconx<9>) to operate in external period reset mode. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 193 dspic33epxxgs50x family bit 7-6 dtc<1:0>: dead-time control bits 11 = reserved 10 = dead-time function is disabled 01 = negative dead time is actively applied for complementary output mode 00 = positive dead time is actively applied for all output modes bit 5-4 unimplemented: read as 0 bit 3 mtbs: master time base select bit 1 = pwmx generator uses the secondary master time base for synchronization and the clock source for the pwmx generation logic (if secondary time base is available) 0 = pwmx generator uses the primary master time base for synchronization and the clock source for the pwmx generation logic bit 2 cam: center-aligned mode enable bit ( 2 , 3 , 4 ) 1 = center-aligned mode is enabled 0 = edge-aligned mode is enabled bit 1 xpres: external pwmx reset control bit ( 5 ) 1 = current-limit source resets the time base for this pwmx generator if it is in independent time base mode 0 = external pins do not affect the pwmx time base bit 0 iue: immediate update enable bit 1 = updates to the active duty cycle, phase offset, dead-time and local time base period registers are immediate 0 = updates to the active duty cycle, phase offset, dead-time and local time base period registers are synchronized to the local pwmx time base register 15-12: pwmconx: pw mx control register (x = 1 to 5) (continued) note 1: software must clear the interrupt status here and in the corresponding ifsx bit in the interrupt controller. 2: the independent time base mode (itb = 1 ) must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 3: these bits should not be changed after the pwmx is enabled by setting pten = 1 (ptcon<15>). 4: center-aligned mode ignores the least significant 3 bits of the duty cycle, phase and dead-time registers. the highest center-aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest clock. 5: configure clmod = 0 (fclconx<8>) and itb = 1 (pwmconx<9>) to operate in external period reset mode. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 194 ? 2013-2015 microchip technology inc. register 15-13: pdcx: pwmx generator duty cycle register (x = 1 to 5) ( 1 , 2 , 3 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 pdcx<15:0>: pwmx generator duty cycle value bits note 1: in independent pwm mode, the pdcx register controls the pwmxh duty cycle only. in the complementary, redundant and push-pull pwm modes, the pdcx register controls the duty cycle of both the pwmxh and pwmxl. 2: the smallest pulse width that can be generated on the pwmx output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of period C 0x0008. 3: as the duty cycle gets closer to 0% or 100% of the pwmx period (0 to 40 ns, depending on the mode of operation), pwmx duty cycle resolution will increase from 1 to 3 lsbs. register 15-14: sdcx: pwmx secondary duty cycle register (x = 1 to 5) ( 1 , 2 , 3 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 sdcx<15:0>: pwmx secondary duty cycle for pwmxl output pin bits note 1: the sdcx register is used in independent pwm mode only. when used in independent pwm mode, the sdcx register controls the pwmxl duty cycle. 2: the smallest pulse width that can be generated on the pwmx output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of period C 0x0008. 3: as the duty cycle gets closer to 0% or 100% of the pwmx period (0 to 40 ns, depending on the mode of operation), pwmx duty cycle resolution will increase from 1 to 3 lsbs. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 195 dspic33epxxgs50x family register 15-15: phasex: pwmx primary phase-shift register (x = 1 to 5) ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 phasex<15:0>: pwmx phase-shift value or independent time base period for the pwmx generator bits note 1: if pwmconx<9> = 0 , the following applies based on the mode of operation: complementary, redundant and push-pull output mode (ioconx<11:10> = 00 , 01 or 10 ); phasex<15:0> = phase-shift value for pwmxh and pwmxl outputs true independent output mode (ioconx<11:10> = 11 ); phasex<15:0> = phase-shift value for pwmxh only when the phasex/sphasex registers provide the phase shift with respect to the master time base; therefore, the valid range is 0x0000 through period 2: if pwmconx<9> = 1 , the following applies based on the mode of operation: complementary, redundant, and push-pull output mode (ioconx<11:10> = 00 , 01 or 10 ); phasex<15:0> = independent time base period value for pwmxh and pwmxl true independent output mode (ioconx<11:10> = 11 ); phasex<15:0> = independent time base period value for pwmxh only when the phasex/sphasex registers provide the local period, the valid range is 0x0000 through 0xfff8 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 196 ? 2013-2015 microchip technology inc. register 15-16: sphase x: pwmx secondary phase-shift register (x = 1 to 5) ( 1 , 2 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 sphasex<15:0>: secondary phase offset for pwmxl output pin bits (used in independent pwm mode only) note 1: if pwmconx<9> = 0 , the following applies based on the mode of operation: complementary, redundant and push-pull output mode (ioconx<11:10> = 00 , 01 or 10 ); sphasex<15:0> = not used true independent output mode (ioconx<11:10> = 11 ), phasex<15:0> = phase-shift value for pwmxl only 2: if pwmconx<9> = 1 , the following applies based on the mode of operation: complementary, redundant and push-pull output mode (ioconx<11:10> = 00 , 01 or 10 ); sphasex<15:0> = not used true independent output mode (ioconx<11:10> = 11 ); phasex<15:0> = independent time base period value for pwmxl only when the phasex/sphasex registers provide the local period, the valid range of values is 0x0010-0xfff8 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 197 dspic33epxxgs50x family register 15-17: dtrx: pwmx dead-time register (x = 1 to 5) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 d t r x < 1 3 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-0 dtrx<13:0>: unsigned 14-bit dead-time value for pwmx dead-time unit bits register 15-18: altdtrx: pwmx alternat e dead-time register (x = 1 to 5) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 altdtrx<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 altdtrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-0 altdtrx<13:0>: unsigned 14-bit dead-time value for pwmx dead-time unit bits downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 198 ? 2013-2015 microchip technology inc. register 15-19: trgconx: pwmx trigge r control register (x = 1 to 5) r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 trgdiv3 trgdiv2 trgdiv1 trgdiv0 bit 15 bit 8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtm ( 1 ) trgstrt5 trgstrt4 trgstrt3 trgstrt2 trgstrt1 trgstrt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 trgdiv<3:0>: trigger # output divider bits 1111 = trigger output for every 16th trigger event 1110 = trigger output for every 15th trigger event 1101 = trigger output for every 14th trigger event 1100 = trigger output for every 13th trigger event 1011 = trigger output for every 12th trigger event 1010 = trigger output for every 11th trigger event 1001 = trigger output for every 10th trigger event 1000 = trigger output for every 9th trigger event 0111 = trigger output for every 8th trigger event 0110 = trigger output for every 7th trigger event 0101 = trigger output for every 6th trigger event 0100 = trigger output for every 5th trigger event 0011 = trigger output for every 4th trigger event 0010 = trigger output for every 3rd trigger event 0001 = trigger output for every 2nd trigger event 0000 = trigger output for every trigger event bit 11-8 unimplemented: read as 0 bit 7 dtm: dual trigger mode bit ( 1 ) 1 = secondary trigger event is combined with the primary trigger event to create a pwm trigger 0 = secondary trigger event is not combined with the primary trigger event to create a pwm trigger; two separate pwm triggers are generated bit 6 unimplemented: read as 0 bit 5-0 trgstrt<5:0>: trigger postscaler start enable select bits 111111 = wait 63 pwm cycles before generating the first trigger event after the module is enabled 000010 = wait 2 pwm cycles before generating the first trigger event after the module is enabled 000001 = wait 1 pwm cycle before generating the first trigger event after the module is enabled 000000 = wait 0 pwm cycles before generating the first trigger event after the module is enabled note 1: the secondary pwmx generator cannot generate pwm trigger interrupts. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 199 dspic33epxxgs50x family register 15-20: ioconx: pwmx i/o control register (x = 1 to 5) r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 penh penl polh poll pmod1 ( 1 ) pmod0 ( 1 ) ovrenh ovrenl bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ovrdat1 ovrdat0 fltdat1 ( 2 ) fltdat0 ( 2 ) cldat1 ( 2 ) cldat0 ( 2 ) swap osync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 penh: pwmxh output pin ownership bit 1 = pwmx module controls the pwmxh pin 0 = gpio module controls the pwmxh pin bit 14 penl: pwmxl output pin ownership bit 1 = pwmx module controls the pwmxl pin 0 = gpio module controls the pwmxl pin bit 13 polh: pwmxh output pin polarity bit 1 = pwmxh pin is active-low 0 = pwmxh pin is active-high bit 12 poll: pwmxl output pin polarity bit 1 = pwmxl pin is active-low 0 = pwmxl pin is active-high bit 11-10 pmod<1:0>: pwmx i/o pin mode bits ( 1 ) 11 = pwmx i/o pin pair is in the true independent output mode 10 = pwmx i/o pin pair is in the push-pull output mode 01 = pwmx i/o pin pair is in the redundant output mode 00 = pwmx i/o pin pair is in the complementary output mode bit 9 ovrenh: override enable for pwmxh pin bit 1 = ovrdat1 provides data for output on the pwmxh pin 0 = pwmx generator provides data for the pwmxh pin bit 8 ovrenl: override enable for pwmxl pin bit 1 = ovrdat0 provides data for output on the pwmxl pin 0 = pwmx generator provides data for the pwmxl pin bit 7-6 ovrdat<1:0>: data for pwmxh, pwmxl pins if override is enabled bits if overenh = 1 , ovrdat1 provides data for the pwmxh pin if overenl = 1 , ovrdat0 provides data for the pwmxl pin bit 5-4 fltdat<1:0>: state for pwmxh and pwmxl pins if fltmod<1:0> are enabled bits ( 2 ) ifltmod (fclconx<15>) = 0 : normal fault mode: if fault is active, then fltdat1 provides the state for the pwmxh pin. if fault is active, then fltdat0 provides the state for the pwmxl pin. ifltmod (fclconx<15>) = 1 : independent fault mode: if current limit is active, then fltdat1 provides the state for the pwmxh pin. if fault is active, then fltdat0 provides the state for the pwmxl pin. note 1: these bits should not be changed after the pwmx module is enabled (pten = 1 ). 2: state represents the active/inactive state of the pwmx depending on the polh and poll bits settings. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 200 ? 2013-2015 microchip technology inc. bit 3-2 cldat<1:0>: state for pwmxh and pwmxl pins if clmod is enabled bits ( 2 ) ifltmod (fclconx<15>) = 0 : normal fault mode: if current limit is active, then cldat1 provides the state for the pwmxh pin. if current limit is active, then cldat0 provides the state for the pwmxl pin. ifltmod (fclconx<15>) = 1 : independent fault mode: cldat<1:0> bits are ignored. bit 1 swap: swap pwmxh and pwmxl pins bit 1 = pwmxh output signal is connected to the pwmxl pins; pwmxl output signal is connected to the pwmxh pins 0 = pwmxh and pwmxl pins are mapped to their respective pins bit 0 osync: output override synchronization bit 1 = output overrides via the ovrdat<1:0> bits are synchronized to the pwmx time base 0 = output overrides via the ovrdat<1:0> bits occur on the next cpu clock boundary register 15-20: ioconx: pw mx i/o control register (x = 1 to 5) (continued) note 1: these bits should not be changed after the pwmx module is enabled (pten = 1 ). 2: state represents the active/inactive state of the pwmx depending on the polh and poll bits settings. register 15-21: trigx: pwmx primary trigger compare value register (x = 1 to 5) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgcmp<12:5> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 trgcmp<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 trgcmp<12:0>: trigger compare value bits when the primary pwmx functions in the local time base, this register contains the compare values that can trigger the adc module. bit 2-0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 201 dspic33epxxgs50x family register 15-22: fclconx: pwmx fau lt current-limit control register (x = 1 to 5) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifltmod clsrc4 clsrc3 clsrc2 clsrc1 clsrc0 clpol ( 1 ) clmod bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltsrc4 fltsrc3 fltsrc2 fltsrc1 fltsrc0 fltpol ( 1 ) fltmod1 fltmod0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ifltmod: independent fault mode enable bit 1 = independent fault mode: current-limit input maps fltdat1 to the pwmxh output and the fault input maps fltdat0 to the pwmxl output; the cldat<1:0> bits are not used for override functions 0 = normal fault mode: current-limit mode maps cldat<1:0> bits to the pwmxh and pwmxl outputs; the pwm fault mode maps fltdat<1:0> to the pwmxh and pwmxl outputs bit 14-10 clsrc<4:0>: current-limit control signal source select for pwmx generator bits 11111 = reserved 10001 = reserved 10000 = analog comparator 4 01111 = analog comparator 3 01110 = analog comparator 2 01101 = analog comparator 1 01100 = fault 12 01011 = fault 11 01010 = fault 10 01001 = fault 9 01000 = fault 8 00111 = fault 7 00110 = fault 6 00101 = fault 5 00100 = fault 4 00011 = fault 3 00010 = fault 2 00001 = fault 1 00000 = reserved bit 9 clpol: current-limit polarity for pwmx generator bit ( 1 ) 1 = the selected current-limit source is active-low 0 = the selected current-limit source is active-high bit 8 clmod: current-limit mode enable for pwmx generator bit 1 = current-limit mode is enabled 0 = current-limit mode is disabled note 1: these bits should be changed only when pten = 0 (ptcon<15>). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 202 ? 2013-2015 microchip technology inc. bit 7-3 fltsrc<4:0>: fault control signal source select for pwmx generator bits 11111 = reserved 10001 = reserved 10000 = analog comparator 4 01111 = analog comparator 3 01110 = analog comparator 2 01101 = analog comparator 1 01100 = fault 12 01011 = fault 11 01010 = fault 10 01001 = fault 9 01000 = fault 8 00111 = fault 7 00110 = fault 6 00101 = fault 5 00100 = fault 4 00011 = fault 3 00010 = fault 2 00001 = fault 1 00000 = reserved bit 2 fltpol: fault polarity for pwmx generator bit ( 1 ) 1 = the selected fault source is active-low 0 = the selected fault source is active-high bit 1-0 fltmod<1:0>: fault mode for pwmx generator bits 11 = fault input is disabled 10 = reserved 01 = the selected fault source forces the pwmxh, pwmxl pins to fltdatx values (cycle) 00 = the selected fault source forces the pwmxh, pwmxl pins to fltdatx values (latched condition) register 15-22: fclconx: pwmx fau lt current-limit control register (x = 1 to 5) (continued) note 1: these bits should be changed only when pten = 0 (ptcon<15>). register 15-23: strigx: pwmx secondary trigger compare value register (x = 1 to 5) ( 1 ) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 strgcmp<12:5> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 strgcmp<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 strgcmp<12:0>: secondary trigger compare value bits when the secondary pwmx functions in the local time base, this register contains the compare values that can trigger the adc module. bit 2-0 unimplemented: read as 0 note 1: strigx cannot generate the pwm trigger interrupts. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 203 dspic33epxxgs50x family register 15-24: lebconx: pwmx leading-edge blanking (leb) control register (x = 1 to 5) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 phr phf plr plf fltleben clleben bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 b c h ( 1 ) bcl ( 1 ) bphh bphl bplh bpll bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 phr: pwmxh rising edge trigger enable bit 1 = rising edge of pwmxh will trigger the leading-edge blanking counter 0 = leading-edge blanking ignores the rising edge of pwmxh bit 14 phf: pwmxh falling edge trigger enable bit 1 = falling edge of pwmxh will trigger the leading-edge blanking counter 0 = leading-edge blanking ignores the falling edge of pwmxh bit 13 plr: pwmxl rising edge trigger enable bit 1 = rising edge of pwmxl will trigger the leading-edge blanking counter 0 = leading-edge blanking ignores the rising edge of pwmxl bit 12 plf: pwmxl falling edge trigger enable bit 1 = falling edge of pwmxl will trigger the leading-edge blanking counter 0 = leading-edge blanking ignores the falling edge of pwmxl bit 11 fltleben: fault input leading-edge blanking enable bit 1 = leading-edge blanking is applied to the selected fault input 0 = leading-edge blanking is not applied to the selected fault input bit 10 clleben: current-limit leading-edge blanking enable bit 1 = leading-edge blanking is applied to the selected current-limit input 0 = leading-edge blanking is not applied to the selected current-limit input bit 9-6 unimplemented: read as 0 bit 5 bch: blanking in selected blanking signal high enable bit ( 1 ) 1 = state blanking (of current-limit and/or fault input signals) when the selected blanking signal is high 0 = no blanking when the selected blanking signal is high bit 4 bcl: blanking in selected blanking signal low enable bit ( 1 ) 1 = state blanking (of current-limit and/or fault input signals) when the selected blanking signal is low 0 = no blanking when the selected blanking signal is low bit 3 bphh: blanking in pwmxh high enable bit 1 = state blanking (of current-limit and/or fault input signals) when the pwmxh output is high 0 = no blanking when the pwmxh output is high bit 2 bphl: blanking in pwmxh low enable bit 1 = state blanking (of current-limit and/or fault input signals) when the pwmxh output is low 0 = no blanking when the pwmxh output is low note 1: the blanking signal is selected via the blanksel<3:0> bits in the auxconx register. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 204 ? 2013-2015 microchip technology inc. bit 1 bplh: blanking in pwmxl high enable bit 1 = state blanking (of current-limit and/or fault input signals) when the pwmxl output is high 0 = no blanking when the pwmxl output is high bit 0 bpll: blanking in pwmxl low enable bit 1 = state blanking (of current-limit and/or fault input signals) when the pwmxl output is low 0 = no blanking when the pwmxl output is low register 15-24: lebconx: pwmx leading-edge blanking (leb) control register (x = 1 to 5) (continued) note 1: the blanking signal is selected via the blanksel<3:0> bits in the auxconx register. register 15-25: lebdlyx: pwmx leading-edge blanking delay register (x = 1 to 5) u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 leb<8:5> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 leb<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-3 leb<8:0>: leading-edge blanking delay for current-limit and fault inputs bits the value is in 8.32 ns increments. bit 2-0 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 205 dspic33epxxgs50x family register 15-26: auxconx: pwmx auxili ary control register (x = 1 to 5) r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 hrpdis hrddis blanksel3 blanksel2 blanksel1 blanksel0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chopsel3 chopsel2 chopsel1 chopsel0 chophen choplen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 hrpdis: high-resolution pwmx period disable bit 1 = high-resolution pwmx period is disabled to reduce power consumption 0 = high-resolution pwmx period is enabled bit 14 hrddis: high-resolution pwmx duty cycle disable bit 1 = high-resolution pwmx duty cycle is disabled to reduce power consumption 0 = high-resolution pwmx duty cycle is enabled bit 13-12 unimplemented: read as 0 bit 11-8 blanksel<3:0>: pwmx state blank source select bits the selected state blank signal will block the current-limit and/or fault input signals (if enabled via the bch and bcl bits in the lebconx register). 1001 = reserved 1000 = reserved 0111 = reserved 0110 = reserved 0101 = pwm5h is selected as the state blank source 0100 = pwm4h is selected as the state blank source 0011 = pwm3h is selected as the state blank source 0010 = pwm2h is selected as the state blank source 0001 = pwm1h is selected as the state blank source 0000 = no state blanking bit 7-6 unimplemented: read as 0 bit 5-2 chopsel<3:0>: pwmx chop clock source select bits the selected signal will enable and disable (chop) the selected pwmx outputs. 1001 = reserved 1000 = reserved 0111 = reserved 0110 = reserved 0101 = pwm5h is selected as the chop clock source 0100 = pwm4h is selected as the chop clock source 0011 = pwm3h is selected as the chop clock source 0010 = pwm2h is selected as the chop clock source 0001 = pwm1h is selected as the chop clock source 0000 = chop clock generator is selected as the chop clock source bit 1 chophen: pwmxh output chopping enable bit 1 = pwmxh chopping function is enabled 0 = pwmxh chopping function is disabled bit 0 choplen: pwmxl output chopping enable bit 1 = pwmxl chopping function is enabled 0 = pwmxl chopping function is disabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 206 ? 2013-2015 microchip technology inc. register 15-27: pwmcapx: pwmx primary time base capture register (x = 1 to 5) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwmcap<12:5> ( 1 , 2 , 3 , 4 ) bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 u-0 u-0 u-0 pwmcap<4:0> ( 1 , 2 , 3 , 4 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 pwmcap<12:0>: pwmx primary time base capture value bits ( 1 , 2 , 3 , 4 ) the value in this register represents the captured pwmx time base value when a leading edge is detected on the current-limit input. bit 2-0 unimplemented: read as 0 note 1: the capture feature is only available on a primary output (pwmxh). 2: this feature is active only after leb processing on the current-limit input signal is complete. 3: the minimum capture resolution is 8.32 ns. 4: this feature can be used when the xpres bit (pwmconx<1>) is set to 0 . downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 207 dspic33epxxgs50x family 16.0 serial peripheral interface (spi) the spi module is a synchronous serial interface, useful for communicating with other peripherals or microcontroller devices. these peripheral devices can be serial eeproms, shift registers, display drivers, adc converters, etc. the spi module is compatible with motorola ? spi and siop interfaces. the dspic33epxxgs50x device family offers two spi modules on a single device. these modules, which are designated as spi1 and spi2, are functionally identical. the spix module takes advantage of the peripheral pin select (pps) feature to allow for greater flexibility in pin configuration. the spix serial interface consis ts of four pins, as follows: sdix: serial data input sdox: serial data output sckx: shift clock input or output ssx /fsyncx: active-low slave select or frame synchronization i/o pulse the spix module can be configured to operate with two, three or four pins. in 3-pin mode, ssx is not used. in 2-pin mode, neither sdox nor ssx is used. figure 16-1 illustrates the block diagram of the spix module in standard and enhanced modes. figure 16-1: spix module block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to serial peripheral interface (spi) (ds70005185) in the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. note: in this section, the spi modules are referred to together as spix, or separately as spi1 and spi2. special function registers follow a similar notation. for example, spixcon refers to the control register for the spi1 and spi2 modules. internal data bus sdix sdox ssx /fsyncx sckx bit 0 shift control edge select f p primary 1:1/4/16/64 enable prescaler sync control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock note 1: in standard mode, the fifo is only one-level deep. clock control secondary prescaler 1:1 to 1:8 spixsr 8-level fifo receive buffer (1) 8-level fifo transmit buffer (1) spixbuf downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 208 ? 2013-2015 microchip technology inc. 16.1 spi helpful tips 1. in frame mode, if there is a possibility that the master may not be initialized before the slave: a) if frmpol (spixcon2<13>) = 1 , use a pull-down resistor on ssx . b) if frmpol = 0 , use a pull-up resistor on ssx . 2. in non-framed 3-wire mode (i.e., not using ssx from a master): a) if ckp (spixcon1<6>) = 1 , always place a pull-up resistor on ssx . b) if ckp = 0 , always place a pull-down resistor on ssx . 3. frmen (spixcon2<15>) = 1 and ssen (spixcon1<7>) = 1 are exclusive and invalid. in frame mode, sckx is continuous and the frame sync pulse is active on the ssx pin, which indicates the start of a data frame. 4. in master mode only, set the smp bit (spixcon1<9>) to a 1 for the fastest spix data rate possible. the smp bit can only be set at the same time or after the msten bit (spixcon1<5>) is set. to avoid invalid slave read data to the master, the users master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. it is always advisable to preload the spixbuf transmit register in advance of the next master transaction cycle. spixbuf is transferred to the spix shift register and is empty once the data transmission begins. 16.2 spi resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 16.2.1 key resources serial peripheral interface (spi) (ds70005185) in the dspic33/pic24 family reference manual code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools note: this ensures that the first frame transmission after initialization is not shifted or corrupted. note: this will ensure that during power-up and initialization, the master/slave will not lose synchronization due to an errant sckx transition that would cause the slave to accumulate data shift errors for both transmit and receive, appearing as corrupted data. note: not all third-party devices support frame mode timing. refer to the spix specifications in section 26.0 electrical characteristics for details. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 209 dspic33epxxgs50x family 16.3 spi control registers register 16-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 spien spisidl spibec2 spibec1 spibec0 bit 15 bit 8 r/w-0 r/c-0, hs r/w-0 r/w-0 r/w-0 r/w-0 r-0, hs, hc r-0, hs, hc srmpt spirov srxmpt sisel2 s isel1 sisel0 spitbf spirbf bit 7 bit 0 legend: c = clearable bit u = unimplemented bit, read as 0 r = readable bit w = writable bit hs = hardware settable bit hc = hard ware clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables the module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables the module bit 14 unimplemented: read as 0 bit 13 spisidl: spix stop in idle mode bit 1 = discontinues the module operation when device enters idle mode 0 = continues the module operation in idle mode bit 12-11 unimplemented: read as 0 bit 10-8 spibec<2:0>: spix buffer element count bits (valid in enhanced buffer mode) master mode: number of spix transfers that are pending. slave mode: number of spix transfers that are unread. bit 7 srmpt: spix shift register (spixsr) empty bit (valid in enhanced buffer mode) 1 = spix shift register is empty and ready to send or receive the data 0 = spix shift register is not empty bit 6 spirov: spix receive overflow flag bit 1 = a new byte/word is completely received and discarded; the user application has not read the previous data in the spixbuf register 0 = no overflow has occurred bit 5 srxmpt: spix receive fifo empty bit (valid in enhanced buffer mode) 1 = rx fifo is empty 0 = rx fifo is not empty bit 4-2 sisel<2:0>: spix buffer interrupt mode bits (valid in enhanced buffer mode) 111 = interrupt when the spix transmit buffer is full (spitbf bit is set) 110 = interrupt when the last bit is shifted into spixsr, and as a result, the tx fifo is empty 101 = interrupt when the last bit is shifted out of spixsr and the transmit is complete 100 = interrupt when one data is shifted into the spixsr, and as a result, the tx fifo has one open memory location 011 = interrupt when the spix receive buffer is full (spirbf bit is set) 010 = interrupt when the spix receive buffer is 3/4 or more full 001 = interrupt when data is available in the receive buffer (srmpt bit is set) 000 = interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty (srxmpt bit is set) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 210 ? 2013-2015 microchip technology inc. bit 1 spitbf: spix transmit buffer full status bit 1 = transmit has not yet started, spixtxb is full 0 = transmit has started, spixtxb is empty standard buffer mode: automatically set in hardware when the core writes to the spixbuf location, loading spixtxb. automatically cleared in hardware when the spix module transfers data from spixtxb to spixsr. enhanced buffer mode: automatically set in hardware when the cpu writes to the spixbuf location, loading the last available buffer location. automatically cleared in hardware when a buffer location is available for a cpu write operation. bit 0 spirbf: spix receive buffer full status bit 1 = receive is complete, spixrxb is full 0 = receive is incomplete, spixrxb is empty standard buffer mode: automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when the core reads the spixbuf location, reading spixrxb. enhanced buffer mode: automatically set in hardware when spix transfers data from spixsr to the buffer, filling the last unread buffer location. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. register 16-1: spixstat: spix status and control register (continued) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 211 dspic33epxxgs50x family register 16-2: spixcon1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dissck dissdo mode16 smp cke ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ( 2 ) ckp msten spre2 ( 3 ) spre1 ( 3 ) spre0 ( 3 ) ppre1 ( 3 ) ppre0 ( 3 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 dissck: disable sckx pin bit (spix master modes only) 1 = internal spix clock is disabled, pin functions as i/o 0 = internal spix clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data is sampled at the end of data output time 0 = input data is sampled at the middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit ( 1 ) 1 = serial output data changes on transition from active clock state to idle clock state (refer to bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (refer to bit 6) bit 7 ssen: slave select enable bit (slave mode) ( 2 ) 1 = ssx pin is used for slave mode 0 = ssx pin is not used by the module; pin is controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in framed spi modes. program this bit to 0 for framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to the value of 1:1. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 212 ? 2013-2015 microchip technology inc. bit 4-2 spre<2:0>: secondary prescale bits (master mode) ( 3 ) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) ( 3 ) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 16-2: spixcon1: spix control register 1 (continued) note 1: the cke bit is not used in framed spi modes. program this bit to 0 for framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to the value of 1:1. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 213 dspic33epxxgs50x family register 16-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 frmdly spiben bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support is enabled (ssx pin is used as the frame sync pulse input/output) 0 = framed spix support is disabled bit 14 spifsd: frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol: frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as 0 bit 1 frmdly: frame sync pulse edge select bit 1 = frame sync pulse coincides with the first bit clock 0 = frame sync pulse precedes the first bit clock bit 0 spiben: enhanced buffer enable bit 1 = enhanced buffer is enabled 0 = enhanced buffer is disabled (standard mode) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 214 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 215 dspic33epxxgs50x family 17.0 inter-integrated circuit (i 2 c) the dspic33epxxgs50x family of devices contains two inter-integrated circuit (i 2 c) modules: i2c1 and i2c2. the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: the sclx/asclx pin is clock the sdax/asdax pin is data the i 2 c module offers the following key features: i 2 c interface supporting both master and slave modes of operation i 2 c slave mode supports 7 and 10-bit addressing i 2 c master mode supports 7 and 10-bit addressing i 2 c port allows bidirectional transfers between master and slaves serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly system management bus (smbus) support alternate i 2 c pin mapping (asclx/asdax) 17.1 i 2 c resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 17.1.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to inter-integrated circuit (i 2 c) (ds70000195) in the dspic33/ pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 216 ? 2013-2015 microchip technology inc. figure 17-1: i2cx block diagram (x = 1 or 2) internal data bus sclx/asclx sdax/asdax shift match detect start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control f p /2 start and stop bit generation acknowledge generation collision detect i2cxconh i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv i2cxadd i2cxconl write read downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 217 dspic33epxxgs50x family 17.2 i 2 c control registers register 17-1: i2cxconl: i2 cx control register low r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen i2csidl sclrel strict a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module; all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as 0 bit 13 i2csidl: i2cx stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write 0 to initiate stretch and write 1 to release clock). hardware is clear at the beginning of every slave data byte transmission. hardware is clear at the end of every slave address byte reception. hardware is clear at the end of every slave data byte reception. if stren = 0 : bit is r/s (i.e., software can only write 1 to release clock). hardware is clear at the beginning of every slave data byte transmission. hardware is clear at the end of every slave address byte reception. bit 11 strict: strict i2cx reserved address enable bit 1 = strict reserved addressing is enabled: in slave mode, the device will nack any reserved address. in master mode, the device is allowed to generate addresses within the reserved address space. 0 = reserved addressing is acknowledged: in slave mode, the device will ack any reserved address. in master mode, the device should not address a slave device with a reserved address. bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with smbus specification 0 = disables smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in i2cxrsr (module is enab led for reception) 0 = general call address is disabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 218 ? 2013-2015 microchip technology inc. bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with the sclrel bit. 1 = enables software or receives clock stretching 0 = disables software or receives clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits ackdt data bit; hardware is clear at the end of the master acknowledge sequence 0 = acknowledge sequence is not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c; hardware is clear at the end of the eighth bit of the master receive data byte 0 = receive sequence is not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on sdax and sclx pins; hardware is clear at the end of the mast er stop sequence 0 = stop condition is not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiates repeated start condition on sdax and sclx pins; hardware is clear at the end of the master repeated start sequence 0 = repeated start condition is not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins; hardware is clear at the end of the master start sequence 0 = start condition is not in progress register 17-1: i2cxconl: i2cx co ntrol register low (continued) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 219 dspic33epxxgs50x family register 17-2: i2cxconh: i2 cx control register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as 0 bit 6 pcie: stop condition interrupt enable bit (i 2 c slave mode only) 1 = enables interrupt on detection of stop condition 0 = stop detection interrupts are disabled bit 5 scie: start condition interrupt enable bit (i 2 c slave mode only) 1 = enables interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled bit 4 boen: buffer overwrite enable bit (i 2 c slave mode only) 1 = i2cxrcv is updated and ack is generated for a received address/data byte, ignoring the state of the i2cov only if the rbf bit = 0 0 = i2cxrcv is only updated when i2cov is clear bit 3 sdaht: sdax hold time selection bit 1 = minimum of 300 ns hold time on sdax after the falling edge of sclx 0 = minimum of 100 ns hold time on sdax after the falling edge of sclx bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) 1 = enables slave bus collision interrupts 0 = slave bus collision interrupts are disabled if the rising edge of sclx and sdax is sampled low when the module is in a high state, the bcl bit is set and the bus goes idle. this detection mode is only valid during data and ack transmit sequences. bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of sclx for a matching received address byte, the sclrel (i2cxconl<12>) bit will be cleared and sclx will be held low 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of sclx for a received data byte, the slave hardware clears the sclrel (i2cxconl<12>) bit and sclx is held low 0 = data holding is disabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 220 ? 2013-2015 microchip technology inc. register 17-3: i2cxstat: i2cx status register r-0, hsc r-0, hsc r-0, hsc u-0 u-0 r/c-0, hs r-0, hsc r-0, hsc ackstat trstat acktim bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit 0 = bit is cleared x = bit is unknown -n = value at por 1 = bit is set u = unimplemented bit, read as 0 bit 15 ackstat: acknowledge status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = nack was received from slave 0 = ack was received from slave hardware is set or clear at the end of a slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware is set at the beginning of master transmission. hardware is clear at the end of slave acknowledge. bit 13 acktim: acknowledge time status bit (i 2 c slave mode only) 1 = i 2 c bus is an acknowledge sequence, set on the 8th falling edge of sclx 0 = not an acknowledge sequence, cleared on the 9th rising edge of sclx bit 12-11 unimplemented: read as 0 bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no bus collision detected hardware is set at detection of a bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware is set when address matches the general call address. hardware is clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware is set at the match of the 2nd byte of the matched 10-bit address. hardware is clear at stop detection. bit 7 iwcol: i2cx write collision detect bit 1 = an attempt to write to the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware is set at the occurrence of a write to i2cxtrn while busy (cleared by software). bit 6 i2cov: i2cx receive overflow flag bit 1 = a byte was received while the i2cxrcv register was still holding the previous byte 0 = no overflow hardware is set at an attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (i 2 c slave mode only) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was a device address hardware is clear at a device address match. hardware is set by reception of a slave byte. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 221 dspic33epxxgs50x family bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware is set or clear when a start, repeated start or stop is detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware is set or clear when a start, repeated start or stop is detected. bit 2 r_w: read/write information bit (i 2 c slave mode only) 1 = read C indicates data transfer is output from the slave 0 = write C indicates data transfer is input to the slave hardware is set or clear after reception of an i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive is complete, i2cxrcv is full 0 = receive is not complete, i2cxrcv is empty hardware is set when i2cxrcv is written with a received byte. hardware is clear when so ftware reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit is in progress, i2cxtrn is full 0 = transmit is complete, i2cxtrn is empty hardware is set when software writes to i2cxtrn. hardware is clear at completion of a data transmission. register 17-3: i2cxstat: i2cx status register (continued) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 222 ? 2013-2015 microchip technology inc. register 17-4: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 amsk<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9-0 amsk<9:0>: address mask select bits for 10-bit address: 1 = enables masking for bit ax of incoming message address; bit match is not required in this position 0 = disables masking for bit ax; bit match is required in this position for 7-bit address (i2cxmsk<6:0> only): 1 = enables masking for bit ax + 1 of incoming message address; bit match is not required in this positi on 0 = disables masking for bit ax + 1; bit match is required in this position downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 223 dspic33epxxgs50x family 18.0 universal asynchronous receiver transmitter (uart) the dspic33epxxgs50x family of devices contains two uart modules. the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspic33epxxgs50x device family. the uart is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, lin/j2602, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins, and also includes an irda ? encoder and decoder. the primary features of the uartx module are: full-duplex, 8 or 9-bit data transmission through the uxtx and uxrx pins even, odd or no parity options (for 8-bit data) one or two stop bits hardware flow control option with uxcts and uxrts pins fully integrated baud rate generator with 16-bit prescaler baud rates ranging from 4.375 mbps to 67 bps in 16x mode at 70 mips baud rates ranging from 17.5 mbps to 267 bps in 4x mode at 70 mips 4-deep first-in first-out (fifo) transmit data buffer 4-deep fifo receive data buffer parity, framing and buffer overrun error detection support for 9-bit mode with address detect (9th bit = 1 ) transmit and receive interrupts a separate interrupt for all uartx error conditions loopback mode for diagnostic support support for sync and break characters support for automatic baud rate detection irda ? encoder and decoder logic 16x baud clock output for irda support a simplified block diagram of the uartx module is shown in figure 18-1 . the uartx module consists of these key hardware elements: baud rate generator asynchronous transmitter asynchronous receiver figure 18-1: uartx simp lified block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to universal asynchro- nous receiver transmitter (uart) (ds70000582) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. uxrx hardware flow control uartx receiver uartx transmitter uxtx baud rate generator uxrts /bclkx uxcts irda ? downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 224 ? 2013-2015 microchip technology inc. 18.1 uart helpful tips 1. in multi-node, direct connect uart networks, uart receive inputs react to the complemen- tary logic level defined by the urxinv bit (uxmode<4>), which defines the idle state, the default of which is logic high (i.e., urxinv = 0 ). because remote devices do not initialize at the same time, it is likely that one of the devices, because the rx line is floating, will trigger a start bit detection and will cause the first byte received, after the device has been initialized, to be invalid. to avoid this situation, the user should use a pull- up or pull-down resistor on the rx pin depending on the value of the urxinv bit. a) if urxinv = 0 , use a pull-up resistor on the uxrx pin. b) if urxinv = 1 , use a pull-down resistor on the uxrx pin. 2. the first character received on a wake-up from sleep mode, caused by activity on the uxrx pin of the uartx module, will be invalid. in sleep mode, peripheral clocks are disabled. by the time the oscillator system has restarted and stabilized from sleep mode, the baud rate bit sampling clock, relative to the incoming uxrx bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected. 18.2 uart resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 18.2.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 225 dspic33epxxgs50x family 18.3 uart control registers register 18-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten ( 1 ) usidl iren ( 2 ) rtsmd u e n 1u e n 0 bit 15 bit 8 r/w-0, hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit ( 1 ) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption is minimal bit 14 unimplemented: read as 0 bit 13 usidl: uartx stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit ( 2 ) 1 = irda encoder and decoder are enabled 0 = irda encoder and decoder are disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as 0 bit 9-8 uen<1:0>: uartx pin enable bits 11 = uxtx, uxrx and bclkx pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclkx pins are controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx continues to sample the uxrx pin, interrupt is generated on the falling edge; bit is cleared in hardware on the following rising edge 0 = no wake-up is enabled bit 6 lpback: uartx loopback mode select bit 1 = enables loopback mode 0 = loopback mode is disabled note 1: refer to universal asynchronous receiver transmitter (uart) (ds70000582) in the dspic33/pic24 family reference manual for information on enabling the uartx module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 226 ? 2013-2015 microchip technology inc. bit 5 abaud: auto-baud enable bit 1 = enables baud rate measurement on the next character C requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement is disabled or completed bit 4 urxinv: uartx receive polarity inversion bit 1 = uxrx idle state is 0 0 = uxrx idle state is 1 bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 18-1: uxmode: uart x mode register (continued) note 1: refer to universal asynchronous receiver transmitter (uart) (ds70000582) in the dspic33/pic24 family reference manual for information on enabling the uartx module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 227 dspic33epxxgs50x family register 18-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 utxbrk utxen ( 1 ) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: c = clearable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: uartx transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr), and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: uartx transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is 0 0 = uxtx idle state is 1 if iren = 1 : 1 =irda ? encoded, uxtx idle state is 1 0 = irda encoded, uxtx idle state is 0 bit 12 unimplemented: read as 0 bit 11 utxbrk: uartx transmit break bit 1 = sends sync break on next transmission C start bit, followed by twelve 0 bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission is disabled or completed bit 10 utxen: uartx transmit enable bit ( 1 ) 1 = transmit is enabled, uxtx pin is controlled by uartx 0 = transmit is disabled, any pending transmission is aborted and buffer is reset; uxtx pin is controlled by the port bit 9 utxbf: uartx transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: uartx receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the uxrsr to the receive buffer; receive buffer has one or more characters note 1: refer to universal asynchronous receiver transmitter (uart) (ds70000582) in the dspic33/ pic24 family reference manual for information on enabling the uartx module for transmit operation. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 228 ? 2013-2015 microchip technology inc. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (clear/read-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed; clearing a previously set oerr bit ( 1 ? 0 transition) resets the receiver buffer and the uxrsr to the empty state bit 0 urxda: uartx receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 18-2: u x sta: uart x status and control register (continued) note 1: refer to universal asynchronous receiver transmitter (uart) (ds70000582) in the dspic33/ pic24 family reference manual for information on enabling the uartx module for transmit operation. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 229 dspic33epxxgs50x family 19.0 high-speed, 12-bit analog-to-digital converter (adc) dspic33epxxgs50x devices have a high-speed, 12-bit analog-to-digital converter (adc) that features a low conversion latency, high resolution and over- sampling capabilities to improve performance in ac/dc, dc/dc power converters. 19.1 features overview the high speed, 12-bit multiple sars analog-to-digital converter (adc) includes the following features: five adc cores: four dedicated cores and one shared (common) core user-configurable resolution of up to 12 bits for each core up to 3.25 msps conversion rate per channel at 12-bit resolution low-latency conversion up to 22 analog input channels, with a separate 16-bit conversion result register for each input conversion result can be formatted as unsigned or signed data, on a per channel basis, for all channels single-ended and pseudo-differential conversions are available on all adc cores simultaneous sampling of up to 5 analog inputs channel scan capability multiple conversion trigger options for each core, including: - pwm1 through pwm5 (primary and secondary triggers, and current-limit event trigger) - pwm special event trigger - timer1/timer2 period match - output compare 1 and event trigger - external pin trigger event (adtrg31) - software trigger two integrated digital comparators with dedicated interrupts: - multiple comparison options - assignable to specific analog inputs two oversampling filters with dedicated interrupts: - provide increased resolution - assignable to a specific analog input the module consists of five independent sar adc cores. simplified block diagrams of the multiple sars 12-bit adc are shown in figure 19-1 , figure 19-2 and figure 19-3 . the analog inputs (channels) are connected through multiplexers and switches to the sample-and-hold (s&h) circuit of each adc core. the core uses the channel information (the output format, the measure- ment mode and the input number) to process the analog sample. when conversion is complete, the result is stored in the result buffer for the specific analog input, and passed to the digital filter and digital comparator if they were configured to use data from this particular channel. the adc module can sample up to five inputs at a time (four inputs from the dedicated sar cores and one from the shared sar core). if multiple adc inputs request conversion on the shared core, the module will convert them in a sequential manner, starting with the lowest order input. the adc provides each analog input the ability to specify its own trigger source. this capability allows the adc to sample and convert analog inputs that are associated with pwm generators operating on independent time bases. note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to 12-bit high-speed, multiple sars a/d converter (adc) (ds70005213) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 230 ? 2013-2015 microchip technology inc. figure 19-1: adc module block diagram voltage reference clock selection (clksel<1:0>) av dd av ss instruction clock frc aux reference reference reference output data clock clock clock output data output data digital comparator 0 adcmp0 interrupt digital comparator 1 adcmp1 interrupt digital filter 0 adfl0dat adcbuf0 adcbuf1 adcbuf21 adcan0 interrupt adcan1 interrupt adcan21 interrupt adfltr0 interrupt dedicated an1 an4 an21 note 1: pga1, pga2 and band gap reference (v bg ) are internal analog inputs and ar e not available on device pins. 2: if the dedicated core uses an alternate channel, then shared core function cannot be used. 3: an0alt and an1alt are not available on dspic33epxxgs502 devices. pga2 (1) an1alt (3) pga1 (1) an0alt (3) an7 an0 adc core 1 (2) an18 dedicated adc core 0 (2) shared adc core clock reference clock output data an2 v bg reference (1) an11 reference clock output data dedicated an3 adc core 3 (2) an15 digital filter 1 adfl1dat adfltr1 interrupt (refsel<2:0>) adc core 2 (2) dedicated divider (clkdiv<5:0>) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 231 dspic33epxxgs50x family figure 19-2: dedicated core s 0 to 3 block diagram figure 19-3: shared core block diagram sample- and-hold 12-bit sar adc selection (diffx) (1) positive input alternate positive input av ss + C adc core clock divider reference output data clock trigger stops sampling negative input negative input pgax note 1: the diffx bit for the corresponding positive input channel must be set in order to use the negative differential input. positive input selection (cxchs<1:0>) (adcs<6:0> bits) shared sample- and-hold an4 an21 + analog channel number from current trigger 12-bit sar adc core clock divider reference clock output data sampling time (shradc<6:0> bits) adc shrsamc<9:0> selection (diffx) (1) av ss C an9 (1) negative input note 1: differential-mode conversion is not available for the shared adc core in dspic33epxxgs502 devices. for all other devices, the diffx bit for the corresponding positive input channel must be set to use an9 as the negative differential input. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 232 ? 2013-2015 microchip technology inc. 19.2 analog-to-digital converter resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 19.2.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools register 19-1: adcon1l: adc control register 1 low r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 adon ( 1 ) a d s i d l bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adon: adc enable bit ( 1 ) 1 = adc module is enabled 0 = adc module is off bit 14 unimplemented: read as 0 bit 13 adsidl: adc stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6-3 reserved: maintain as 0 bit 2-0 unimplemented: read as 0 note 1: set the adon bit only after the adc module has been configured. changing adc configuration bits whe n adon = 1 will result in unpredictable behavior. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 233 dspic33epxxgs50x family register 19-2: adcon1h: adc control register 1 high r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bit 15 bit 8 r/w-0 r/w-1 r/w-1 r-0 r-0 r-0 r-0 r-0 form shrres1 shrres0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 reserved: maintain as 0 bit 7 form: fractional data output format bit 1 = fractional 0 = integer bit 6-5 shrres<1:0>: shared adc core resolution selection bits 11 = 12-bit resolution 10 = 10-bit resolution 01 = 8-bit resolution 00 = 6-bit resolution bit 4-0 reserved: maintain as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 234 ? 2013-2015 microchip technology inc. register 19-3: adcon2l: adc control register 2 low r/w-0 r/w-0 r-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 refcie refercie e i e n shreisel2 ( 1 ) shreisel1 ( 1 ) shreisel0 ( 1 ) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 shradcs6 shradcs5 shradcs4 shradcs3 shradcs2 shradcs1 shradcs0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 refcie: band gap and reference voltage ready common interrupt enable bit 1 = common interrupt will be generated when the band gap will become ready 0 = common interrupt is disabled for the band gap ready event bit 14 refercie: band gap or reference voltage error common interrupt enable bit 1 = common interrupt will be generated when a band gap or reference voltage error is detected 0 = common interrupt is disabled for the band gap and reference voltage error event bit 13 reserved: maintain as 0 bit 12 eien: early interrupts enable bit 1 = the early interrupt feature is enabled for the input channel interrupts (when the eistatx flag is set) 0 = the individual interrupts are generated when conversion is done (when the anxrdy flag is set) bit 11 reserved: maintain as 0 bit 10-8 shreisel<2:0>: shared core early interrupt time selection bits ( 1 ) 111 = early interrupt is set and interrupt is generated 8 t adcore clocks prior to when the data is ready 110 = early interrupt is set and interrupt is generated 7 t adcore clocks prior to when the data is ready 101 = early interrupt is set and interrupt is generated 6 t adcore clocks prior to when the data is ready 100 = early interrupt is set and interrupt is generated 5 t adcore clocks prior to when the data is ready 011 = early interrupt is set and interrupt is generated 4 t adcore clocks prior to when the data is ready 010 = early interrupt is set and interrupt is generated 3 t adcore clocks prior to when the data is ready 001 = early interrupt is set and interrupt is generated 2 t adcore clocks prior to when the data is ready 000 = early interrupt is set and interrupt is generated 1 t adcore clock prior to when the data is ready bit 7 unimplemented: read as 0 bit 6-0 shradcs<6:0>: shared adc core input clock divider bits these bits determine the number of t coresrc (source clock periods) for one shared t adcore (core clock period). 1111111 = 254 source clock periods 0000011 = 6 source clock periods 0000010 = 4 source clock periods 0000001 = 2 source clock periods 0000000 = 2 source clock periods note 1: for the 6-bit shared adc core resolution (shrres<1:0> = 00 ), the shreisel<2:0> settings, from 100 to 111 , are not valid and should not be used. for the 8-bit shared adc core resolution (shrres<1:0> = 01 ), the shreisel<2:0> settings, 110 and 111 , are not valid and should not be used. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 235 dspic33epxxgs50x family register 19-4: adcon2h: adc control register 2 high r-0, hsc r-0, hsc r-0 r-0 r-0 r-0 r/w-0 r/w-0 refrdy referr shrsamc9 shrsamc8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 shrsamc7 shrsamc6 shrsamc5 shrsamc4 shrsamc3 shrsamc2 shrsamc1 shrsamc0 bit 7 bit 0 legend: r = reserved bit u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 refrdy: band gap and reference voltage ready flag bit 1 = band gap is ready 0 = band gap is not ready bit 14 referr: band gap or reference voltage error flag bit 1 = band gap was removed after the adc module was enabled (adon = 1 ) 0 = no band gap error was detected bit 13-10 reserved: maintain as 0 bit 9-0 shrsamc<9:0>: shared adc core sample time selection bits these bits specify the number of shared adc core clock periods (t adcore ) for the shared adc core sample time. 1111111111 = 1025 t adcore 0000000001 = 3 t adcore 0000000000 = 2 t adcore downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 236 ? 2013-2015 microchip technology inc. register 19-5: adcon3l: adc control register 3 low r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0, hsc r/w-0 r-0, hsc refsel2 refsel1 refsel0 suspend suspcie susprdy shrsamp cnvrtch bit 15 bit 8 r/w-0 r-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 swlctrg swctrg cnvchsel5 cnvchsel4 cnvchsel3 cnvchsel2 cnvchsel1 cnvchsel0 bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 refsel<2:0>: adc reference voltage selection bits 001 - 111 = unimplemented: do not use bit 12 suspend: all adc cores triggers disable bit 1 = all new trigger events for all adc cores are disabled 0 = all adc cores can be triggered bit 11 suspcie: suspend all adc cores common interrupt enable bit 1 = common interrupt will be generated when adc core triggers are suspended (suspend bit = 1 ) and all previous conversions are finished (susprdy bit becomes set) 0 = common interrupt is not generated for suspend adc cores event bit 10 susprdy: all adc cores suspended flag bit 1 = all adc cores are suspended (suspend bit = 1 ) and have no conversions in progress 0 = adc cores have previous conversions in progress bit 9 shrsamp: shared adc core sampling direct control bit this bit should be used with the individual channel conversion trigger controlled by the cnvrtch bit. it connects an analog input, specified by the cnvchsel<5:0> bits, to the shared adc core and allows extending the sampling time. this bit is not controlled by hardware and must be cleared before the conversion starts (setting cnvrtch to 1 ). 1 = shared adc core samples an analog input specified by the cnvchsel<5:0> bits 0 = sampling is controlled by the shared adc core hardware bit 8 cnvrtch: software individual channel conversion trigger bit 1 = single trigger is generated for an analog input specified by the cnvchsel<5:0> bits; when the bit is set, it is automatically cleared by hardware on the next instruction cycle 0 = next individual channel conversion trigger can be generated bit 7 swlctrg: software level-sensitive common trigger bit 1 = triggers are continuously generated for all channels with the software, level-sensitive common trigger selected as a source in the adtrigxl and adtrigxh registers 0 = no software, level-sensitive common triggers are generated bit 6 swctrg: software common trigger bit 1 = single trigger is generated for all channels with the software, common trigger selected as a source in the adtrigxl and adtrigxh registers; when the bit is set, it is automatically cleared by hardware on the next instruction cycle 0 = ready to generate the next software, common trigger bit 5-0 cnvchsel <5:0>: channel number selection for software individual channel conversion trigger bits these bits define a channel to be converted when the cnvrtch bit is set. value v refh v refl 000 av dd av ss downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 237 dspic33epxxgs50x family register 19-6: adcon3h: adc control register 3 high r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 clksel1 clksel0 clkdiv5 clkdiv4 clkdiv3 clkdiv2 clkdiv1 clkdiv0 bit 15 bit 8 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 shren c 3 e nc 2 e nc 1 e nc 0 e n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 clksel<1:0>: adc module clock source selection bits 11 = apll 10 = frc 01 = f osc (system clock x 2) 00 = f sys (system clock) bit 13-8 clkdiv<5:0>: adc module clock source divider bits the divider forms a t coresrc clock used by all adc cores (shared and dedicated) from the t src adc module clock source selected by the clksel<2:0> bits. then, each adc core individually divides the t coresrc clock to get a core-specific t adcore clock using the adcs<6:0> bits in the adcorexh register or the shradcs<6:0> bits in the adcon2l register. 111111 = 64 source clock periods 000011 = 4 source clock periods 000010 = 3 source clock periods 000001 = 2 source clock periods 000000 = 1 source clock period bit 7 shren: shared adc core enable bit 1 = shared adc core is enabled 0 = shared adc core is disabled bit 6-4 unimplemented: read as 0 bit 3 c3en: dedicated adc core 3 enable bits 1 = dedicated adc core 3 is enabled 0 = dedicated adc core 3 is disabled bit 2 c2en: dedicated adc core 2 enable bits 1 = dedicated adc core 2 is enabled 0 = dedicated adc core 2 is disabled bit 1 c1en: dedicated adc core 1 enable bits 1 = dedicated adc core 1 is enabled 0 = dedicated adc core 1 is disabled bit 0 c0en: dedicated adc core 0 enable bits 1 = dedicated adc core 0 is enabled 0 = dedicated adc core 0 is disabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 238 ? 2013-2015 microchip technology inc. register 19-7: adcon4l: adc control register 4 low u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 synctrg3 synctrg2 synctrg1 synctrg0 bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 samc3en samc2en samc1en samc0en bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11 synctrg3: dedicated adc core 3 trigger synchronization bit 1 = all triggers are synchronized with the core source clock (t coresrc ) 0 = the adc core triggers are not synchronized bit 10 synctrg2: dedicated adc core 2 trigger synchronization bit 1 = all triggers are synchronized with the core source clock (t coresrc ) 0 = the adc core triggers are not synchronized bit 9 synctrg1: dedicated adc core 1 trigger synchronization bit 1 = all triggers are synchronized with the core source clock (t coresrc ) 0 = the adc core triggers are not synchronized bit 8 synctrg0: dedicated adc core 0 trigger synchronization bit 1 = all triggers are synchronized with the core source clock (t coresrc ) 0 = the adc core triggers are not synchronized bit 7-4 unimplemented: read as 0 bit 3 samc3en: dedicated adc core 3 conversion delay enable bit 1 = after trigger, the conversion will be delayed and the adc core will continue sampling during the time specified by the samc<9:0> bits in the adcore3l register 0 = after trigger, the sampling will be stopped immediately and the conversion will be started on th e next core clock cycle bit 2 samc2en: dedicated adc core 2 conversion delay enable bit 1 = after trigger, the conversion will be delayed and the adc core will continue sampling during the time specified by the samc<9:0> bits in the adcore2l register 0 = after trigger, the sampling will be stopped immediately and the conversion will be started on th e next core clock cycle bit 1 samc1en: dedicated adc core 1 conversion delay enable bit 1 = after trigger, the conversion will be delayed and the adc core will continue sampling during the time specified by the samc<9:0> bits in the adcore1l register 0 = after trigger, the sampling will be stopped immediately and the conversion will be started on th e next core clock cycle bit 0 samc0en: dedicated adc core 0 conversion delay enable bit 1 = after trigger, the conversion will be delayed and the adc core will continue sampling during the time specified by the samc<9:0> bits in the adcore0l register 0 = after trigger, the sampling will be stopped immediately and the conversion will be started on th e next core clock cycle downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 239 dspic33epxxgs50x family register 19-8: adcon4h: adc control register 4 high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c3chs1 c3chs0 c2chs1 c2chs0 c1chs1 c1chs0 c0chs1 c0chs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-6 c3chs<1:0>: dedicated adc core 3 input channel selection bits 1x = reserved 01 = an15 (differential negative input when diff3 (admod0l<7>) = 1 ) 00 = an3 bit 5-4 c2chs<1:0>: dedicated adc core 2 input channel selection bits 11 = reserved 10 = v ref band gap 01 = an11 (differential negative input when diff2 (admod0l<5>) = 1 ) 00 = an2 bit 3-2 c1chs<1:0>: dedicated adc core 1 input channel selection bits 11 = an1alt 10 = pga2 01 = an18 (differential negative input when diff1 (admod0l<3>) = 1 ) 00 = an1 bit 1-0 c0chs<1:0>: dedicated adc core 0 input channel selection bits 11 = an0alt 10 = pga1 01 = an7 (differential negative input when diff0 (admod0l<1>) = 1 ) 00 = an0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 240 ? 2013-2015 microchip technology inc. register 19-9: adcon5l: adc control register 5 low r-0, hsc u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc shrrdy c3rdy c2rdy c1rdy c0rdy bit 15 bit 8 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 shrpwr c3pwr c2pwr c1pwr c0pwr bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 shrrdy: shared adc core ready flag bit 1 = adc core is powered and ready for operation 0 = adc core is not ready for operation bit 14-12 unimplemented: read as 0 bit 11 c3rdy: dedicated adc core 3 ready flag bit 1 = adc core is powered and ready for operation 0 = adc core is not ready for operation bit 10 c2rdy: dedicated adc core 2 ready flag bit 1 = adc core is powered and ready for operation 0 = adc core is not ready for operation bit 9 c1rdy: dedicated adc core 1 ready flag bit 1 = adc core is powered and ready for operation 0 = adc core is not ready for operation bit 8 c0rdy: dedicated adc core 0 ready flag bit 1 = adc core is powered and ready for operation 0 = adc core is not ready for operation bit 7 shrpwr: shared adc core x power enable bit 1 = adc core x is powered 0 = adc core x is off bit 6-4 unimplemented: read as 0 bit 3 c3pwr: dedicated adc core 3 power enable bit 1 = adc core is powered 0 = adc core is off bit 2 c2pwr: dedicated adc core 2 power enable bit 1 = adc core is powered 0 = adc core is off bit 1 c1pwr: dedicated adc core 1 power enable bit 1 = adc core is powered 0 = adc core is off bit 0 c0pwr: dedicated adc core 0 power enable bit 1 = adc core is powered 0 = adc core is off downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 241 dspic33epxxgs50x family register 19-10: adcon5h: a dc control register 5 high u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 warmtime3 warmtime2 warmtime1 warmtime0 bit 15 bit 8 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 shrcie c3cie c2cie c1cie c0cie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 warmtime<3:0>: adc dedicated core x power-up delay bits these bits determine the power-up delay in the number of the core source clock periods (t coresrc ) for all adc cores. 1111 = 32768 source clock periods 1110 = 16384 source clock periods 1101 = 8192 source clock periods 1100 = 4096 source clock periods 1011 = 2048 source clock periods 1010 = 1024 source clock periods 1001 = 512 source clock periods 1000 = 256 source clock periods 0111 = 128 source clock periods 0110 = 64 source clock periods 0101 = 32 source clock periods 0100 = 16 source clock periods 00xx = 16 source clock periods bit 7 shrcie: shared adc core ready common interrupt enable bit 1 = common interrupt will be generated when adc core is powered and ready for operation 0 = common interrupt is disabled for an adc core ready event bit 6-4 unimplemented: read as 0 bit 3 c3cie: dedicated adc core 3 ready common interrupt enable bit 1 = common interrupt will be generated when adc core 3 is powered and ready for operation 0 = common interrupt is disabled for an adc core 3 ready event bit 2 c2cie: dedicated adc core 2 ready common interrupt enable bit 1 = common interrupt will be generated when adc core 2 is powered and ready for operation 0 = common interrupt is disabled for an adc core 2 ready event bit 1 c1cie: dedicated adc core 1 ready common interrupt enable bit 1 = common interrupt will be generated when adc core 1 is powered and ready for operation 0 = common interrupt is disabled for an adc core 1 ready event bit 0 c0cie: dedicated adc core 0 ready common interrupt enable bit 1 = common interrupt will be generated when adc core 0 is powered and ready for operation 0 = common interrupt is disabled for an adc core 0 ready event downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 242 ? 2013-2015 microchip technology inc. register 19-11: adcorexl: dedicated adc core x control register low (x = 0 to 3) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 samc<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 samc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9-0 samc<9:0>: dedicated adc core x conversion delay selection bits these bits determine the time between the trigger event and the start of conversion in the number of the core clock periods (t adcore ). during this time, the adc core x still continues sampling. this feature is enabled by the samcxen bits in the adcon4l register. 1111111111 = 1025 t adcore 0000000001 = 3 t adcore 0000000000 = 2 t adcore downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 243 dspic33epxxgs50x family register 19-12: adcorexh: dedicated adc core x control register high (x = 0 to 3) ( 1 ) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 eisel2 eisel1 eisel0 res1 res0 bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-10 eisel<2:0>: adc core x early interrupt time selection bits 111 = early interrupt is set and an interrupt is generated 8 t adcore clocks prior to when the data is ready 110 = early interrupt is set and an interrupt is generated 7 t adcore clocks prior to when the data is ready 101 = early interrupt is set and an interrupt is generated 6 t adcore clocks prior to when the data is ready 100 = early interrupt is set and an interrupt is generated 5 t adcore clocks prior to when the data is ready 011 = early interrupt is set and an interrupt is generated 4 t adcore clocks prior to when the data is ready 010 = early interrupt is set and an interrupt is generated 3 t adcore clocks prior to when the data is ready 001 = early interrupt is set and an interrupt is generated 2 t adcore clocks prior to when the data is ready 000 = early interrupt is set and an interrupt is generated 1 t adcore clock prior to when the data is ready bit 9-8 res<1:0>: adc core x resolution selection bits 11 = 12-bit resolution 10 = 10-bit resolution 01 = 8-bit resolution 00 = 6-bit resolution bit 7 unimplemented: read as 0 bit 6-0 adcs<6:0>: adc core x input clock divider bits these bits determine the number of source clock periods (t coresrc ) for one core clock period (t adcore ). 1111111 = 254 source clock periods 0000011 = 6 source clock periods 0000010 = 4 source clock periods 0000001 = 2 source clock periods 0000000 = 2 source clock periods note 1: for the 6-bit adc core resolution (res<1:0> = 00 ), the eisel<2:0> bits settings, from 100 to 111 , are not valid and should not be used. for the 8-bit adc core resolution (res<1:0> = 01 ), the eisel<2:0> bits settings, 110 and 111 , are not valid and should not be used. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 244 ? 2013-2015 microchip technology inc. register 19-13: adlvltrgl: adc level-sen sitive trigger control register low r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 lvlen<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lvlen<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 lvlen<15:0>: level trigger for corresponding analog input enable bits 1 = input trigger is level-sensitive 0 = input trigger is edge-sensitive register 19-14: adlvltrgh: adc level-sens itive trigger control register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lvlen<21:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 lvlen<21:16>: level trigger for corresponding analog input enable bits 1 = input trigger is level-sensitive 0 = input trigger is edge-sensitive downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 245 dspic33epxxgs50x family register 19-15: adeiel: adc early interrupt enable register low r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 eien<15:0>: early interrupt enable for corresponding analog inputs bits 1 = early interrupt is enabled for the channel 0 = early interrupt is disabled for the channel register 19-16: adeieh: adc earl y interrupt enable register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien<21:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 eien<21:16>: early interrupt enable for corresponding analog inputs bits 1 = early interrupt is enabled for the channel 0 = early interrupt is disabled for the channel downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 246 ? 2013-2015 microchip technology inc. register 19-17: adeistatl: adc early interrupt status register low r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eistat<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eistat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 eistat<15:0>: early interrupt status for corresponding analog inputs bits 1 = early interrupt was generated 0 = early interrupt was not generated since the last adcbufx read register 19-18: adeistath: adc early interrupt status register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eistat<21:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 eistat<21:16>: early interrupt status for corresponding analog inputs bits 1 = early interrupt was generated 0 = early interrupt was not generated since the last adcbufx read downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 247 dspic33epxxgs50x family register 19-19: admod0l: adc inpu t mode control register 0 low r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff7 sign7 diff6 sign6 diff5 sign5 diff4 sign4 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff3 sign3 diff2 sign2 diff1 sign1 diff0 sign0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-1(odd) diff<7:0>: differential-mode for corresponding analog inputs bits 1 = channel is differential 0 = channel is single-ended bit 14-0 (even) sign<7:0>: output data sign for corresponding analog inputs bits 1 = channel output data is signed 0 = channel output data is unsigned register 19-20: admod0h: adc input mode control register 0 high r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff15 sign15 diff14 sign14 diff13 sign13 diff12 sign12 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff11 sign11 diff10 sign10 diff9 sign9 diff8 sign8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-1(odd) diff<15:8>: differential-mode for corresponding analog inputs bits 1 = channel is differential 0 = channel is single-ended bit 14-0 (even) sign<15:8>: output data sign for corresponding analog inputs bits 1 = channel output data is signed 0 = channel output data is unsigned downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 248 ? 2013-2015 microchip technology inc. register 19-21: admod1l: adc inpu t mode control register 1 low u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 diff21 sign21 diff20 sign20 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff19 sign19 diff18 sign18 diff17 sign17 diff16 sign16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-1(odd) diff<21:16>: differential-mode for corresponding analog inputs bits 1 = channel is differential 0 = channel is single-ended bit 10-0 (even) sign<21:16>: output data sign for corresponding analog inputs bits 1 = channel output data is signed 0 = channel output data is unsigned downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 249 dspic33epxxgs50x family register 19-22: adiel: adc interrupt enable register low r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ie<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ie<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 ie<15:0>: common interrupt enable bits 1 = common and individual interrupts are enabled for the corresponding channel 0 = common and individual interrupts are disabled for the corresponding channel register 19-23: adieh: adc interrupt enable register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ie21 ie20 ie19 ie18 ie17 ie16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 ie<21:16>: common interrupt enable bits 1 = common and individual interrupts are enabled for the corresponding channel 0 = common and individual interrupts are disabled for the corresponding channel downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 250 ? 2013-2015 microchip technology inc. register 19-24: adstatl: adc data ready status register low r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc an<15:8>rdy bit 15 bit 8 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc an<7:0>rdy bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 an<15:0>rdy: common interrupt enable for corresponding analog inputs bits 1 = channel conversion result is ready in the corresponding adcbufx register 0 = channel conversion result is not ready register 19-25: adstath: adc data ready status register high u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc an<21:16>rdy bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 an<21:16>rdy: common interrupt enable for corresponding analog inputs bits 1 = channel conversion result is ready in the corresponding adcbufx register 0 = channel conversion result is not ready downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 251 dspic33epxxgs50x family register 19-26: adtrigxl: adc channel trigger x selection register low (x = 0 to 5) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc(4x+1)<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc(4x)<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 trgsrc(4x+1)<4:0>: trigger source selection for corresponding analog inputs bits 11111 = adtrg31 11110 = reserved 11101 = reserved 11100 = reserved 11011 = reserved 11010 = pwm generator 3 current-limit trigger 11001 = pwm generator 2 current-limit trigger 11000 = pwm generator 1 current-limit trigger 10111 = reserved 10110 = output compare 1 trigger 10101 = reserved 10100 = reserved 10011 = reserved 10010 = reserved 10001 = pwm generator 3 secondary trigger 10000 = pwm generator 2 secondary trigger 01111 = pwm generator 1 secondary trigger 01110 = pwm secondary special event trigger 01101 = timer2 period match 01100 = timer1 period match 01011 = reserved 01010 = reserved 01001 = reserved 01000 = reserved 00111 = pwm generator 3 primary trigger 00110 = pwm generator 2 primary trigger 00101 = pwm generator 1 primary trigger 00100 = pwm special event trigger 00011 = reserved 00010 = level software trigger 00001 = common software trigger 00000 = no trigger is enabled bit 7-5 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 252 ? 2013-2015 microchip technology inc. bit 4-0 trgsrc(4x)<4:0>: trigger source selection for corresponding analog inputs bits 11111 = adtrg31 11110 = reserved 11101 = reserved 11100 = reserved 11011 = reserved 11010 = pwm generator 3 current-limit trigger 11001 = pwm generator 2 current-limit trigger 11000 = pwm generator 1 current-limit trigger 10111 = reserved 10110 = output compare 1 trigger 10101 = reserved 10100 = reserved 10011 = reserved 10010 = reserved 10001 = pwm generator 3 secondary trigger 10000 = pwm generator 2 secondary trigger 01111 = pwm generator 1 secondary trigger 01110 = pwm secondary special event trigger 01101 = timer2 period match 01100 = timer1 period match 01011 = reserved 01010 = reserved 01001 = reserved 01000 = reserved 00111 = pwm generator 3 primary trigger 00110 = pwm generator 2 primary trigger 00101 = pwm generator 1 primary trigger 00100 = pwm special event trigger 00011 = reserved 00010 = level software trigger 00001 = common software trigger 00000 = no trigger is enabled register 19-26: adtrigxl: adc channel trigger x selection register low (x = 0 to 5) (continued) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 253 dspic33epxxgs50x family register 19-27: adtrigxh: adc channel trigger x selection register high (x = 0 to 5) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc(4x+3)<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc(4x+2)<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 trgsrc(4x+3)<4:0>: trigger source selection for corresponding analog inputs bits 11111 = adtrg31 11110 = reserved 11101 = reserved 11100 = reserved 11011 = reserved 11010 = pwm generator 3 current-limit trigger 11001 = pwm generator 2 current-limit trigger 11000 = pwm generator 1 current-limit trigger 10111 = reserved 10110 = output compare 1 trigger 10101 = reserved 10100 = reserved 10011 = reserved 10010 = reserved 10001 = pwm generator 3 secondary trigger 10000 = pwm generator 2 secondary trigger 01111 = pwm generator 1 secondary trigger 01110 = pwm secondary special event trigger 01101 = timer2 period match 01100 = timer1 period match 01011 = reserved 01010 = reserved 01001 = reserved 01000 = reserved 00111 = pwm generator 3 primary trigger 00110 = pwm generator 2 primary trigger 00101 = pwm generator 1 primary trigger 00100 = pwm special event trigger 00011 = reserved 00010 = level software trigger 00001 = common software trigger 00000 = no trigger is enabled bit 7-5 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 254 ? 2013-2015 microchip technology inc. bit 4-0 trgsrc(4x+2)<4:0>: trigger source selection for corresponding analog inputs bits 11111 = adtrg31 11110 = reserved 11101 = reserved 11100 = reserved 11011 = reserved 11010 = pwm generator 3 current-limit trigger 11001 = pwm generator 2 current-limit trigger 11000 = pwm generator 1 current-limit trigger 10111 = reserved 10110 = output compare 1 trigger 10101 = reserved 10100 = reserved 10011 = reserved 10010 = reserved 10001 = pwm generator 3 secondary trigger 10000 = pwm generator 2 secondary trigger 01111 = pwm generator 1 secondary trigger 01110 = pwm secondary special event trigger 01101 = timer2 period match 01100 = timer1 period match 01011 = reserved 01010 = reserved 01001 = reserved 01000 = reserved 00111 = pwm generator 3 primary trigger 00110 = pwm generator 2 primary trigger 00101 = pwm generator 1 primary trigger 00100 = pwm special event trigger 00011 = reserved 00010 = level software trigger 00001 = common software trigger 00000 = no trigger is enabled register 19-27: adtrigxh: adc channel trigger x selection register high (x = 0 to 5) (continued) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 255 dspic33epxxgs50x family register 19-28: adcal0l: adc calibration register 0 low r-0, hsc u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cal1rdy cal1skip cal1diff cal1en cal1run bit 15 bit 8 r-0, hsc u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cal0rdy cal0skip cal0diff cal0en cal0run bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cal1rdy: dedicated adc core 1 calibration status flag bit 1 = dedicated adc core 1 calibration is finished 0 = dedicated adc core 1 calibration is in progress bit 14-12 unimplemented: read as 0 bit 11 cal1skip: dedicated adc core 1 calibration bypass bit 1 = after power-up, the dedicated adc core 1 will not be calibrated 0 = after power-up, the dedicated adc core 1 will be calibrated bit 10 cal1diff: dedicated adc core 1 differential-mode calibration bit 1 = dedicated adc core 1 will be calibrated in differential input mode 0 = dedicated adc core 1 will be calibrated in single-ended input mode bit 9 cal1en: dedicated adc core 1 calibration enable bit 1 = dedicated adc core 1 calibration bits (calxrdy, calxskip, calxdiff and calxrun) can be accessed by software 0 = dedicated adc core 1 calibration bits are disabled bit 8 cal1run: dedicated adc core 1 calibration start bit 1 = if this bit is set by software, the dedicated adc core 1 calibration cycle is started; this bit is automatically cleared by hardware 0 = software can start the next calibration cycle bit 7 cal0rdy: dedicated adc core 0 calibration status flag bit 1 = dedicated adc core 0 calibration is finished 0 = dedicated adc core 0 calibration is in progress bit 6-4 unimplemented: read as 0 bit 3 cal0skip: dedicated adc core 0 calibration bypass bit 1 = after power-up, the dedicated adc core 0 will not be calibrated 0 = after power-up, the dedicated adc core 0 will be calibrated bit 2 cal0diff: dedicated adc core 0 differential-mode calibration bit 1 = dedicated adc core 0 will be calibrated in differential input mode 0 = dedicated adc core 0 will be calibrated in single-ended input mode bit 1 cal0en: dedicated adc core 0 calibration enable bit 1 = dedicated adc core 0 calibration bits (calxrdy, calxskip, calxdiff and calxrun) can be accessed by software 0 = dedicated adc core 0 calibration bits are disabled bit 0 cal0run: dedicated adc core 0 calibration start bit 1 = if this bit is set by software, the dedicated adc core 0 calibration cycle is started; this bit is automatically cleared by hardware 0 = software can start the next calibration cycle downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 256 ? 2013-2015 microchip technology inc. register 19-29: adcal0h: adc cal ibration register 0 high r-0, hsc u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cal3rdy cal3skip cal3diff cal3en cal3run bit 15 bit 8 r-0, hsc u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cal2rdy cal2skip cal2diff cal2en cal2run bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cal3rdy: dedicated adc core 3 calibration status flag bit 1 = dedicated adc core 3 calibration is finished 0 = dedicated adc core 3 calibration is in progress bit 14-12 unimplemented: read as 0 bit 11 cal3skip: dedicated adc core 3 calibration bypass bit 1 = after power-up, the dedicated adc core 3 will not be calibrated 0 = after power-up, the dedicated adc core 3 will be calibrated bit 10 cal3diff: dedicated adc core 3 differential-mode calibration bit 1 = dedicated adc core 3 will be calibrated in differential input mode 0 = dedicated adc core 3 will be calibrated in single-ended input mode bit 9 cal3en: dedicated adc core 3 calibration enable bit 1 = dedicated adc core 3 calibration bits (calxrdy, calxskip, calxdiff and calxrun) can be accessed by software 0 = dedicated adc core 3 calibration bits are disabled bit 8 cal3run: dedicated adc core 3 calibration start bit 1 = if this bit is set by software, the dedicated adc core 3 calibration cycle is started; this bit is automatically cleared by hardware 0 = software can start the next calibration cycle bit 7 cal2rdy: dedicated adc core 2 calibration status flag bit 1 = dedicated adc core 2 calibration is finished 0 = dedicated adc core 2 calibration is in progress bit 6-4 unimplemented: read as 0 bit 3 cal2skip: dedicated adc core 2 calibration bypass bit 1 = after power-up, the dedicated adc core 2 will not be calibrated 0 = after power-up, the dedicated adc core 2 will be calibrated bit 2 cal2diff: dedicated adc core 2 differential-mode calibration bit 1 = dedicated adc core 2 will be calibrated in differential input mode 0 = dedicated adc core 2 will be calibrated in single-ended input mode bit 1 cal2en: dedicated adc core 2 calibration enable bit 1 = dedicated adc core 2 calibration bits (calxrdy, calxskip, calxdiff and calxrun) can be accessed by software 0 = dedicated adc core 2 calibration bits are disabled bit 0 cal2run: dedicated adc core 2 calibration start bit 1 = if this bit is set by software, the dedicated adc core 2 calibration cycle is started; this bit is automatically cleared by hardware 0 = software can start the next calibration cycle downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 257 dspic33epxxgs50x family register 19-30: adcal1h: adc cal ibration register 1 high r/w-0, hs u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cshrrdy cshrskip cshrdiff cshren cshrrun bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cshrrdy: shared adc core calibration status flag bit 1 = shared adc core calibration is finished 0 = shared adc core calibration is in progress bit 14-12 unimplemented: read as 0 bit 11 cshrskip: shared adc core calibration bypass bit 1 = after power-up, the shared adc core will not be calibrated 0 = after power-up, the shared adc core will be calibrated bit 10 cshrdiff: shared adc core differential-mode calibration bit 1 = shared adc core will be calibrated in differential input mode 0 = shared adc core will be calibrated in single-ended input mode bit 9 cshren: shared adc core calibration enable bit 1 = shared adc core calibration bits (cshrrdy, cshrskip, cshrdiff and cshrrun) can be accessed by software 0 = shared adc core calibration bits are disabled bit 8 cshrrun: shared adc core calibration start bit 1 = if this bit is set by software, the shared adc core calibration cycle is started; this bit is cleared automatically by hardware 0 = software can start the next calibration cycle bit 7-0 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 258 ? 2013-2015 microchip technology inc. register 19-31: adcmpxcon: adc digital comparator x control register (x = 0 or 1 ) u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc chnl4 chnl3 chnl2 chnl1 chnl0 bit 15 bit 8 r/w-0 r/w-0 r-0, hc, hs r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpen ie stat btwn hihi hilo lohi lolo bit 7 bit 0 legend: hc = hardware clearable bit u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared hs = hardware settable bit bit 15-13 unimplemented: read as 0 bit 12-8 chnl<4:0>: input channel number bits if the comparator has detected an event for a channel, this channel number is written to these bits. 11111 = reserved 10110 = reserved 10101 = an21 10100 = an20 00001 = an1 00000 = an0 bit 7 cmpen: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled and the stat status bit is cleared bit 6 ie: comparator common adc interrupt enable bit 1 = common adc interrupt will be generated if the comparator detects a comparison event 0 = common adc interrupt will not be generated for the comparator bit 5 stat: comparator event status bit this bit is cleared by hardware when the channel number is read from the chnl<4:0> bits. 1 = a comparison event has been detected since the last read of t he chnl<4:0> bits 0 = a comparison event has not been detected since the last read of the chnl<4:0> bits bit 4 btwn: between low/high comparator event bit 1 = generates a comparator event when adcmpxlo adcbufx < adcmpxhi 0 = does not generate a digital comparator event when adcmpxlo adcbufx < adcmpxhi bit 3 hihi: high/high comparator event bit 1 = generates a digital comparator event when adcbufx adcmpxhi 0 = does not generate a digital comparator event when adcbufx adcmpxhi bit 2 hilo: high/low comparator event bit 1 = generates a digital comparator event when adcbufx < adcmpxhi 0 = does not generate a digital comparator event when adcbufx < adcmpxhi bit 1 lohi: low/high comparator event bit 1 = generates a digital comparator event when adcbufx adcmpxlo 0 = does not generate a digital comparator event when adcbufx adcmpxlo bit 0 lolo: low/low comparator event bit 1 = generates a digital comparator event when adcbufx < adcmpxlo 0 = does not generate a digital comparator event when adcbufx < adcmpxlo downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 259 dspic33epxxgs50x family register 19-32: adcmpxenl: adc digital comparator x channel enable register low (x = 0 or 1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpen<15:8> bit 15 bit 8 r/w/0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpen<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 cmpen<15:0>: comparator enable for corresponding input channels bits 1 = conversion result for corresponding channel is used by the comparator 0 = conversion result for corresponding channel is not used by the comparator register 19-33: adcmpxenh: adc digital comparator x channel enable register high (x = 0 or 1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpen<21:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 cmpen<21:16>: comparator enable for corresponding input channels bits 1 = conversion result for corresponding channel is used by the comparator 0 = conversion result for corresponding channel is not used by the comparator downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 260 ? 2013-2015 microchip technology inc. register 19-34: adflxcon: adc di gital filter x control register (x = 0 or 1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0, hsc flen mode1 mode0 ovrsam2 ovrsam1 ovrsam0 ie rdy bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flchsel4 flchsel3 flch sel2 flchsel1 flchsel0 bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 flen: filter enable bit 1 = filter is enabled 0 = filter is disabled and the rdy bit is cleared bit 14-13 mode<1:0>: filter mode bits 11 = averaging mode 10 = reserved 01 = reserved 00 = oversampling mode bit 12-10 ovrsam<2:0>: filter averaging/oversampling ratio bits if mode<1:0> = 00 : 111 = 128x (16-bit result in the adflxdat register is in 12.4 format) 110 = 32x (15-bit result in the adflxdat register is in 12.3 format) 101 = 8x (14-bit result in the adflxdat register is in 12.2 format) 100 = 2x (13-bit result in the adflxdat register is in 12.1 format) 011 = 256x (16-bit result in the adflxdat register is in 12.4 format) 010 = 64x (15-bit result in the adflxdat register is in 12.3 format) 001 = 16x (14-bit result in the adflxdat register is in 12.2 format) 000 = 4x (13-bit result in the adflxdat register is in 12.1 format) if mode<1:0> = 11 (12-bit result in the adflxdat register in all instances) : 111 = 256x 110 = 128x 101 = 64x 100 = 32x 011 = 16x 010 = 8x 001 = 4x 000 = 2x bit 9 ie: filter common adc interrupt enable bit 1 = common adc interrupt will be generated when the filter result will be ready 0 = common adc interrupt will not be generated for the filter bit 8 rdy: oversampling filter data ready flag bit this bit is cleared by hardware when the result is read from the adflxdat register. 1 = data in the adflxdat register is ready 0 = the adflxdat register has been read and new data in the adflxdat register is not ready bit 7-5 unimplemented: read as 0 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 261 dspic33epxxgs50x family bit 4-0 flchsel<4:0>: oversampling filter input channel selection bits 11111 = reserved 10110 = reserved 10101 = an21 10100 = an20 00001 = an1 00000 = an0 register 19-34: adflxcon: adc di gital filter x control register (x = 0 or 1) (continued) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 262 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 263 dspic33epxxgs50x family 20.0 high-speed analog comparator the high-speed analog comparator module monitors current and/or voltage transients that may be too fast for the cpu and adc to capture. 20.1 features overview the smps comparator module offers the following major features: four rail-to-rail analog comparators dedicated 12-bit dac for each analog comparator up to six selectable input sources per comparator: - four external inputs - two internal inputs from the pgax module programmable comparator hysteresis programmable output polarity up to two dac outputs to device pins multiple voltage references for the dac: - external references (extref1 or extref2) -av dd interrupt generation capability functional support for pwmx: - pwmx duty cycle control - pwmx period control - pwmx fault detected note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to high-speed analog comparator module (ds70005128) in the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 264 ? 2013-2015 microchip technology inc. 20.2 module description figure 20-1 shows a functional block diagram of one analog comparator from the high-speed analog comparator module. the analog comparator provides high-speed operation with a typical delay of 15 ns. the negative input of the comparator is always connected to the dacx circuit. the positive input of the compara- tor is connected to an analog multiplexer that selects the desired source pin. the analog comparator input pins are typically shared with pins used by the analog-to-digital converter (adc) module. both the comparator and the adc can use the same pins at the same time. this capability enables a user to measure an input voltage with the adc and detect voltage transients with the comparator. figure 20-1: high-speed analog comp arator x module block diagram cmpxa (1) cmpxc (1) dacx (1) cmppol 01 av dd cmrefx cmpx (1) inselx 12 interrupt cmpxb (1) cmpxd (1) pulse stretcher pwm trigger and dacout1 note 1: x = 1-4 2: extref1 is connected to dac1/dac3. extref2 is connected to dac2/dac4. 3: not available on all devices. status digital filter output buffer pga1out pga2out mux altinp mux (remappable i/o) request extref range extref1 (2) extref2 (2,3) dacoe dacout2 (3) dacoe dbcc bit fdevopt<6> dac1/ dac3 pga1out dac2/ dac4 pga2out pgaoen pgaoen output buffer downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 265 dspic33epxxgs50x family 20.3 module applications this module provides a means for the smps dspic ? dsc devices to monitor voltage and currents in a power conversion application. the ability to detect transient conditions and stimulate the dspic dsc processor and/or peripherals, without requiring the processor and adc to constantly monitor voltages or currents, frees the dspic dsc to perform other tasks. the comparator module has a high-speed comparator and an associated 12-bit dac that provides a programmable reference voltage to the inverting input of the comparator. the polarity of the comparator out- put is user-programmable. the output of the module can be used in the following modes: generate an interrupt trigger an adc sample and convert process truncate the pwmx signal (current limit) truncate the pwmx period (current minimum) disable the pwmx outputs (fault latch) the output of the comparator module may be used in multiple modes at the same time, such as: 1) generate an interrupt, 2) have the adc take a sample and con- vert it, and 3) truncate the pwmx output in response to a voltage being detected beyond its expected value. the comparator module can also be used to wake-up the system from sleep or idle mode when the analog input voltage exceeds the programmed threshold voltage. 20.4 digital-to-analog comparator (dac) each analog comparator has a dedicated 12-bit dac that is used to program the comparator threshold voltage via the cmpxdac register. the dac voltage reference source is selected using the extref and range bits in the cmpxcon register. the extref bit selects either the external voltage ref- erence, extrefx, or an internal source as the voltage reference source. the extrefx input enables users to connect to a voltage reference that better suits their application. the range bit enables av dd as the voltage reference source for the dac when an internal voltage reference is selected. each dacx has an output enable bit, dacoe, in the cmpxcon register that enables the dacx reference voltage to be routed to an external output pin (dacoutx). refer to figure 20-1 for connecting the dacx output voltage to the dacoutx pins. 20.5 pulse stretcher and digital logic the analog comparator can respond to very fast tran- sient signals. after the comparator output is given the desired polarity, the signal is passed to a pulse stretching circuit. the pulse stretching circuit has an asynchronous set function and a delay circuit that ensures the minimum pulse width is three system clock cycles wide to allow the attached circuitry to properly respond to a narrow pulse event. the pulse stretcher circuit is followed by a digital filter. the digital filter is enabled via the fltren bit in the cmpxcon register. the digital filter operates with the clock specified via the fclksel bit in the cmpxcon register. the comparator signal must be stable in a high or low state, for at least three of the selected clock cycles, for it to pass through the digital filter. note: extref2 is not available on all devices. note 1: ensure that multiple dacoe bits are not set in software. the output on the dacoutx pin will be indeterminate if multiple comparators enable the dacx output. 2: dacout2 is not available on all devices. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 266 ? 2013-2015 microchip technology inc. 20.6 hysteresis an additional feature of the module is hysteresis con- trol. hysteresis can be enabled or disabled and its amplitude can be controlled by the hyssel<1:0> bits in the cmpxcon register. three different values are available: 15 mv, 30 mv and 45 mv. it is also possible to select the edge (rising or falling) to which hysteresis is to be applied. hysteresis control prevents the comparator output from continuously changing state because of small perturbations (noise) at the input (see figure 20-2 ). figure 20-2: hyst eresis control 20.7 analog comparator resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page contains the latest updates and additional information. 20.7.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools output input hysteresis range (15 mv/30 mv/45 mv) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 267 dspic33epxxgs50x family register 20-1: cmpxcon: co mparator x control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpon cmpsidl hyssel1 hyssel0 fltren fclksel dacoe bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 hc-0, hs r/w-0 r/w-0 r/w-0 insel1 insel0 extref hyspol cmpstat altinp cmppol range bit 7 bit 0 legend: hc = hardware clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cmpon: comparator operating mode bit 1 = comparator module is enabled 0 = comparator module is disabled (reduces power consumption) bit 14 unimplemented: read as 0 bit 13 cmpsidl: comparator stop in idle mode bit 1 = discontinues module operation when device enters idle mode. 0 = continues module operation in idle mode if a device has multiple comparators, any cmpsidl bit set to 1 disables all comparators while in idle mode. bit 12-11 hyssel<1:0>: comparator hysteresis select bits 11 = 20 mv hysteresis 10 = 10 mv hysteresis 01 = 5 mv hysteresis 00 = no hysteresis is selected bit 10 fltren: digital filter enable bit 1 = digital filter is enabled 0 = digital filter is disabled bit 9 fclksel: digital filter and pulse stretcher clock select bit 1 = digital filter and pulse stretcher operate with the pwm clock 0 = digital filter and pulse stretcher operate with the system clock bit 8 dacoe: dacx output enable bit 1 = dacx analog voltage is connected to the dacoutx pin ( 1 ) 0 = dacx analog voltage is not connected to the dacoutx pin bit 7-6 insel<1:0>: input source select for comparator bits if altinp = 0 , select from comparator inputs: 11 = selects cmpxd input pin 10 = selects cmpxc input pin 01 = selects cmpxb input pin 00 = selects cmpxa input pin if altinp = 1 , select from alternate inputs: 11 = reserved 10 = reserved 01 = selects pga2 output 00 = selects pga1 output note 1: dacoutx can be associated only with a single comparator at any given time. the software m ust ensure that multiple comparators do not enable the dacx output by setting their respective dacoe bit. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 268 ? 2013-2015 microchip technology inc. bit 5 extref: enable external reference bit 1 = external source provides reference to dacx (maximum dac voltage is determined by the ex ternal voltage source) 0 =av dd provides reference to dacx (maximum dac voltage is av dd ) bit 4 hyspol: comparator hysteresis polarity select bit 1 = hysteresis is applied to the falling edge of the comparator output 0 = hysteresis is applied to the rising edge of the comparator output bit 3 cmpstat: comparator current state bit reflects the current output state of comparator x, including the setting of the cmppol bit. bit 2 altinp: alternate input select bit 1 = insel<1:0> bits select alternate inputs 0 = insel<1:0> bits select comparator inputs bit 1 cmppol: comparator output polarity control bit 1 = output is inverted 0 = output is non-inverted bit 0 range: dacx output voltage range select bit 1 = av dd is the maximum dacx output voltage 0 = unimplemented, do not use register 20-1: cmpxcon: comparator x control register (continued) note 1: dacoutx can be associated only with a single comparator at any given time. the software mus t ensure that multiple comparators do not enable the dacx output by setting their respective dacoe bit. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 269 dspic33epxxgs50x family register 20-2: cmpxdac: comparator x dac control register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c m r e f < 1 1 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmref<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-0 cmref<11:0>: comparator reference voltage select bits 111111111111 = ([cmref<11:0>] * (av dd )/4096) volts (extref = 0 ) or ([cmref<11:0>] * (extref)/4096) volts (extref = 1 ) 000000000000 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 270 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 271 dspic33epxxgs50x family 21.0 programmable gain amplifier (pga) the dspic33epxxgs50x family devices have two programmable gain amplifiers (pga1, pga2). the pga is an op amp-based, non-inverting amplifier with user-programmable gains. the output of the pga can be connected to a number of dedicated sample-and- hold inputs of the analog-to-digital converter and/or to the high-speed analog comparator module. the pga has five selectable gains and may be used as a ground referenced amplifier (single-ended) or used with an independent ground reference point. key features of the pga module include: single-ended or independent ground reference selectable gains: 4x, 8x, 16x, 32x and 64x high gain bandwidth rail-to-rail output voltage wide input voltage range figure 21-1: pgax mo dule block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to programmable gain amplifier (pga) (ds70005146) in the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. gain<2:0> = 6 gain of 64x gain<2:0> = 5 gain<2:0> = 4 gain<2:0> = 3 gain<2:0> = 2 ampx C+ pgax calibrations<5:0> pgax negative input pgax positive input gain of 32x gain of 16x gain of 8x gain of 4x pgaxout note 1: x = 1 and 2. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 272 ? 2013-2015 microchip technology inc. 21.1 module description the programmable gain amplifiers are used to amplify small voltages (i.e., voltages across burden/shunt resistors) to improve the signal-to-noise ratio of the measured signal. the pgax output voltage can be read by any of the four dedicated sample-and-hold circuits on the adc module. the output voltage can also be fed to the comparator module for overcurrent/ voltage protection. figure 21-2 shows a functional block diagram of the pgax module. refer to section 19.0 high-speed, 12-bit analog-to-digital converter (adc) and section 20.0 high-speed analog comparator for more interconnection details. the gain of the pgax module is selectable via the gain<2:0> bits in the pgaxcon register. there are five selectable gains, ranging from 4x to 64x. the selpi<2:0> and selni<2:0> bits in the pgaxcon register select one of four positive/negative inputs to the pgax module. for single-ended applications, the selni<2:0> bits will select the ground as the negative input source. to provide an independent ground reference, pgaxn2 and pgaxn3 pins are available as the negative input source to the pgax module. the output voltage of the pgax module can be connected to the dacoutx pin by setting the pgaoen bit in the pgax con register. when the pgaoen bit is enabled, the output voltage of pga1 is connected to dacout1 and pga2 is connected to dacout2. for devices with a single dacoutx pin, the output voltage of pga2 can be connected to dacout1 by configuring the dbcc configuration bit in the fdevopt register (fdevopt<6>). if both the dacx output voltage and pgax output volt- age are connected to the dacoutx pin, the resulting output voltage would be a combination of signals. there is no assigned priority between the pgax module and the dacx module. figure 21-2: pgax f unctional block diagram note 1: not all pga positive/negative inputs are available on all devices. refer to the specific device pinout for available input source pins. C + pgaxp1 (1) pgaxp2 (1) pgaxp3 (1) pgaxp4 (1) selpi<2:0> selni<2:0> gnd pgaxn2 (1) pgaxn3 (1,3) gnd adc s&h pgaxcon (1) pgaxcal (1) pgaen gain<2:0> pgacal<5:0> +C dacx cxchs<1:0> (adcon4h) insel<1:0> (cmpconx) to dacoutx pin (2) pgax (1) note 1: x = 1 and 2. 2: the dacout2 device pin is only available on 64-pin devices. 3: the pgaxn3 input is not available on 28-pin devices. pgaoen downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 273 dspic33epxxgs50x family 21.2 pga resources many useful resources are provided on the main prod- uct page of the microchip website for the devices listed in this data sheet. this product page contains the latest updates and additional information. 21.2.1 key resources code samples application notes software libraries webinars all related dspic33/pic24 family reference manual sections development tools register 21-1: pgaxcon: pgax control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pgaen pgaoen selpi2 selpi1 sel pi0 selni2 selni1 selni0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 gain2 gain1 gain0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pgaen: pgax enable bit 1 = pgax module is enabled 0 = pgax module is disabled (reduces power consumption) bit 14 pgaoen: pgax output enable bit 1 = pgax output is connected to the dacoutx pin 0 = pgax output is not connected to the dacoutx pin bit 13-11 selpi<2:0>: pgax positive input selection bits 111 = reserved 110 = reserved 101 = reserved 100 = reserved 011 = pgaxp4 010 = pgaxp3 001 = pgaxp2 000 = pgaxp1 bit 10-8 selni<2:0>: pgax negative input selection bits 111 = reserved 110 = reserved 101 = reserved 100 = reserved 011 = ground (single-ended mode) 010 = pgaxn3 001 = pgaxn2 000 = ground (single-ended mode) bit 7-3 unimplemented: read as 0 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 274 ? 2013-2015 microchip technology inc. bit 2-0 gain<2:0>: pgax gain selection bits 111 = reserved 110 = gain of 64x 101 = gain of 32x 100 = gain of 16x 011 = gain of 8x 010 = gain of 4x 001 = reserved 000 = reserved register 21-1: pgaxcon: pgax control register (continued) register 21-2: pgaxcal: pg ax calibration register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pgacal<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 pgacal<5:0>: pgax offset calibration bits the calibration values for pga1 and pga2 must be copied from flash addresses, 0x800e48 and 0x800e4c, respectively, into these bits before the module is enabled. refer to the calibration data address table ( table 23-3 ) in section 23.0 special features for more information. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 275 dspic33epxxgs50x family 22.0 constant-current source the constant-current source module is a precision current generator and is used in conjunction with the adc module to measure the resistance of external resistors connected to device pins. 22.1 features overview the constant-current source module offers the following major features: constant-current generator (10 a nominal) internal selectable connection to one of four pins enable/disable bit 22.2 module description figure 22-1 shows a functional block diagram of the constant-current source module. it consists of a precision current generator with a nominal value of 10 a. the module can be enabled and disabled using the isrcen bit in the isrccon register. the output of the current generator is internally connected to a device pin. the dspic33epxxgs50x family can have up to 4 selectable current source pins. the outsel<2:0> bits in the isrccon register allow selection of the target pin. the current source is calibrated during testing. figure 22-1: constant-current source module block diagram note 1: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the dspic33/pic24 family reference man- ual , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for device-specific register and bit information. isrc1 isrc3 m u x outsel<2:0> isrc2 isrc4 isrcen constant-current source downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 276 ? 2013-2015 microchip technology inc. 22.3 current source control register register 22-1: isrccon: constant-current sou rce control register r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 isrcen outsel2 outsel1 outsel0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 isrccal5 isrccal4 isrccal3 isrccal2 isrccal1 isrccal0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 isrcen: constant-current source enable bit 1 = current source is enabled 0 = current source is disabled bit 14-11 unimplemented: read as 0 bit 10-8 outsel<2:0>: output constant-current select bits 111 = reserved 110 = reserved 101 = reserved 100 = input pin, isrc4 (an4) 011 = input pin, isrc3 (an5) 010 = input pin, isrc2 (an6) 001 = input pin, isrc1 (an12) 000 = no output is selected bit 7-6 unimplemented: read as 0 bit 5-0 isrccal<5:0>: constant-current source calibration bits the calibration value must be copied from flash address, 0x800e78, into these bits before the module is enabled. refer to the calibration data address table ( tab l e 2 3- 3 ) in section 23.0 special features for more information. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 277 dspic33epxxgs50x family 23.0 special features the dspic33epxxgs50x family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: flexible configuration watchdog timer (wdt) code protection and codeguard? security jtag boundary scan interface in-circuit serial programming? (icsp?) in-circuit emulation brown-out reset (bor) 23.1 configuration bits in dspic33epxxgs50x family devices, the configu- ration words are implemented as volatile memory. this means that configuration data must be programmed each time the device is powered up. configuration data is stored at the end of the on-chip program memory space, known as the flash configuration words. their specific locations are shown in table 23-1 with detailed descriptions in table 23-2 . the configuration data is automatically loaded from the flash configuration words to the proper configuration shadow registers during device resets. for devices operating in dual partition modes, the bseqx bits (fbtseq<11:0>) determine which panel is the active partition at start-up and the configuration words from that panel are loaded into the configuration shadow registers. when creating applications for these devices, users should always specifically allocate the location of the flash configuration words for configuration data in their code for the compiler. this is to make certain that program code is not stored in this address when the code is compiled. program code executing out of configuration space will cause a device reset. note: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to the related section of the dspic33/pic24 family reference manual , which is available from the microchip web site ( www.microchip.com ). note: configuration data is reloaded on all types of device resets. note: performing a page erase operation on the last page of program memory clears the flash configuration words. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 278 ? 2013-2015 microchip technology inc. table 23-1: configuration register map ( 3 ) name address device memory size (kbytes) bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsec 002b80 16 aivtdis css<2:0> cwrp gss<1:0> gwrp bsen bss<1:0> bwrp 005780 32 00af80 64 fbslim 002b90 16 bslim<12:0> 005790 32 00af90 64 fsign 002b94 16 reserved ( 2 ) 005794 32 00af94 64 foscsel 002b98 16 ieso fnosc<2:0> 005798 32 00af98 64 fosc 002b9c 16 pllken fcksm<1:0> iol1way osciofncposcmd<1:0> 00579c 32 00af9c 64 fwdt 002ba0 16 wdtwin<1:0> windis wdten<1:0> wdtpre wdtpost<3:0> 0057a0 32 00afa0 64 fpor 002ba4 16 reserved ( 1 ) 0057a4 32 00afa4 64 ficd 002ba8 16 b t s w p reserved ( 1 ) jtagen i c s < 1 : 0 > 0057a8 32 00afa8 64 note 1: these bits are reserved and must be programmed as 1 . 2: this bit is reserved and must be programmed as 0 . 3: when operating in dual partition mode, each partition will have dedicated c onfiguration registers. on a device reset, the confi guration values of the active partition are read at start-up, but during a soft swap condition, the configuration settings of the newly active partitio n are ignored. 4: fboot resides in configuration memory space. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 279 dspic33epxxgs50x family fdevopt 002bac 16 d b c c a l t i 2 c 2a l t i 2 c 1r e s e r v e d ( 1 ) pwmlock 0057ac 32 00afac 64 faltreg 002bb0 16 ctxt2 <2:0> ctxt1 <2:0> 0057b0 32 00afb0 64 fbtseq 002bfc 16 ibseq<11:0> bseq<11:0> 0057fc 32 00affc 64 fboot ( 4 ) 801000 btmode<1:0> table 23-1: configuration register map ( 3 ) (continued) name address device memory size (kbytes) bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 note 1: these bits are reserved and must be programmed as 1 . 2: this bit is reserved and must be programmed as 0 . 3: when operating in dual partition mode, each partition will have dedicated c onfiguration registers. on a device reset, the confi guration values of the active partition are read at start-up, but during a soft swap condition, the configuration settings of the newly active partitio n are ignored. 4: fboot resides in configuration memory space. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 280 ? 2013-2015 microchip technology inc. table 23-2: configuration bits description bit field description bss<1:0> boot segment code-protect level bits 11 = boot segment is not code-protected other than bwrp 10 = standard security 0x = high security bsen boot segment control bit 1 = no boot segment is enabled 0 = boot segment size is determined by the bslim<12:0> bits bwrp boot segment write-protect bit 1 = boot segment can be written 0 = boot segment is write-protected bslim<12:0> boot segment flash page address limit bits contains the last active boot segment page. the value to be programmed is the inverted page address, such that programming additional 0 s can only increase the boot segment size (i.e., 0x1ffd = 2 pages or 1024 iw). gss<1:0> general segment code-protect level bits 11 = user program memory is not code-protected 10 = standard security 0x = high security gwrp general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected cwrp configuration segment write-protect bit 1 = configuration data is not write-protected 0 = configuration data is write-protected css<2:0> configuration segment code-protect level bits 111 = configuration data is not code-protected 110 = standard security 10x = enhanced security 0xx = high security btswp bootswp instruction enable/disable bit 1 = bootswp instruction is disabled 0 = bootswp instruction is enabled bseq<11:0> boot sequence number bits (dual partition modes only) relative value defining which partition will be active after device reset; the partition containing a lower boot number will be active. ibseq<11:0> inverse boot sequence number bits (dual partition modes only) the ones complement of bseq<11:0>; must be calculated by the user and written for device programming. if bseqx and ibseqx are not complements of each other, the boot sequence number is considered to be invalid. aivtdis ( 1 ) alternate interrupt vector table bit 1 = alternate interrupt vector table is disabled 0 = alternate interrupt vector table is enabled if intcon2<8> = 1 ieso two-speed oscillator start-up enable bit 1 = starts up device with frc, then automatically switches to the user-selected oscillator source when ready 0 = starts up device with the user-selected oscillator source pwmlock pwmx lock enable bit 1 = certain pwmx registers may only be written after a key sequence 0 = pwmx registers may be written without a key sequence note 1: the boot segment must be present to use the alternate interrupt vector table. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 281 dspic33epxxgs50x family fnosc<2:0> oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdivn) 110 = fast rc oscillator with divide-by-16 101 = low-power rc oscillator (lprc) 100 = reserved; do not use 011 = primary oscillator with pll module (xt + pll, hs + pll, ec + pll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with divide-by-n with pll module (frcpll) 000 = fast rc oscillator (frc) fcksm<1:0> clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way peripheral pin select configuration bit 1 = allows only one reconfiguration 0 = allows multiple reconfigurations osciofnc osc2 pin function bit (except in xt and hs modes) 1 = osc2 is the clock output 0 = osc2 is a general purpose digital i/o pin poscmd<1:0> primary oscillator mode select bits 11 = primary oscillator is disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode wdten<1:0> watchdog timer enable bits 11 = watchdog timer is always enabled (lprc oscillator cannot be disabled; clearing the swdten bit in the rcon register will have no effect) 10 = watchdog timer is enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) 01 = watchdog timer is enabled only while device is active and is disabled while in sleep mode; software control is disabled in this mode 00 = watchdog timer and swdten bit are disabled windis watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode pllken pll lock enable bit 1 = pll lock is enabled 0 = pll lock is disabled wdtpre watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 0001 = 1:2 0000 = 1:1 table 23-2: configuration bits description (continued) bit field description note 1: the boot segment must be present to use the alternate interrupt vector table. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 282 ? 2013-2015 microchip technology inc. wdtwin<1:0> watchdog timer window select bits 11 = wdt window is 25% of the wdt period 10 = wdt window is 37.5% of the wdt period 01 = wdt window is 50% of the wdt period 00 = wdt window is 75% of the wdt period alti2c1 alternate i2c1 pin bit 1 = i2c1 is mapped to the sda1/scl1 pins 0 = i2c1 is mapped to the asda1/ascl1 pins alti2c2 alternate i2c2 pin bit 1 = i2c2 is mapped to the sda2/scl2 pins 0 = i2c2 is mapped to the asda2/ascl2 pins jtagen jtag enable bit 1 = jtag is enabled 0 = jtag is disabled ics<1:0> icd communication channel select bits 11 = communicates on pgec1 and pged1 10 = communicates on pgec2 and pged2 01 = communicates on pgec3 and pged3 00 = reserved, do not use dbcc dacx output cross connection select bit 1 = no cross connection between dac outputs 0 = interconnects dacout1 and dacout2 ctxt1<2:0> alternate working register set 1 interrupt priority leve l (ipl) select bits 111 = reserved 110 = assigned to ipl of 7 101 = assigned to ipl of 6 100 = assigned to ipl of 5 011 = assigned to ipl of 4 010 = assigned to ipl of 3 001 = assigned to ipl of 2 000 = assigned to ipl of 1 ctxt2<2:0> alternate working register set 2 interrupt priority leve l (ipl) select bits 111 = reserved 110 = assigned to ipl of 7 101 = assigned to ipl of 6 100 = assigned to ipl of 5 011 = assigned to ipl of 4 010 = assigned to ipl of 3 001 = assigned to ipl of 2 000 = assigned to ipl of 1 btmode<1:0> boot mode configuration bits 11 = single partition mode 10 = dual partition mode 01 = protected dual partition mode 00 = privileged dual partition mode table 23-2: configuration bits description (continued) bit field description note 1: the boot segment must be present to use the alternate interrupt vector table. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 283 dspic33epxxgs50x family 23.2 device calibration and identification the pgax and current source modules on the dspic33epxxgs50x family devices require calibra- tion data registers to improve performance of the module over a wide operating range. these calibration registers are read-only and are stored in configuration memory space. prior to enabling the module, the calibration data must be read (tblpag and table read instruction) and loaded into their respective sfr registers. the device calibration addresses are shown in table 23-3 . the dspic33epxxgs50x devices have two identifica- tion registers near the end of configuration memory space that store the device id (devid) and device revision (devrev). these registers are used to deter- mine the mask, variant and manufacturing information about the device. these registers are read-only and are shown in register 23-1 and register 23-2 . table 23-3: device calibration addresses ( 1 ) calibration name address bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga1cal 800e48 pga1 calibration data pga2cal 800e4c pga2 calibration data isrccal 800e78 current source calibration data note 1: the calibration data must be copied into its respective registers prior to enabling the module. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 284 ? 2013-2015 microchip technology inc. register 23-1: devid: device id register rrrrrrrr devid<23:16> bit 23 bit 16 rrrrrrrr devid<15:8> bit 15 bit 8 rrrrrrrr devid<7:0> bit 7 bit 0 legend: r = read-only bit u = unimplemented bit bit 23-0 devid<23:0>: device identifier bits register 23-2: devrev: device revision register rrrrrrrr devrev<23:16> bit 23 bit 16 rrrrrrrr devrev<15:8> bit 15 bit 8 rrrrrrrr devrev<7:0> bit 7 bit 0 legend: r = read-only bit u = unimplemented bit bit 23-0 devrev<23:0>: device revision bits downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 285 dspic33epxxgs50x family 23.3 user otp memory dspic33epxxgs50x family devices contain 64 words of user one-time-programmable (otp) memory, located at addresses, 0x800f80 through 0x800ffe. the user otp words can be used for storing checksum, code revisions, product information, such as serial num- bers, system manufacturing dates, manufacturing lot numbers and other application-specific information. these words can only be written once at program time and not at run time; they can be read at run time. 23.4 on-chip voltage regulator all the dspic33epxxgs50x family devices power their core digital logic at a nominal 1.8v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the dspic33epxxgs50x family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. a low-esr (less than 1 ohm) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 23-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in tab le 2 6- 5 , located in section 26.0 electrical characteristics . figure 23-1: conne ctions for the on-chip voltage regulator ( 1 , 2 , 3 ) 23.5 brown-out reset (bor) the brown-out reset (bor) module is based on an internal voltage reference circuit that monitors the reg- ulated supply voltage, v cap . the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on). a bor generates a reset pulse which resets the device. the bor selects the clock source based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is 1 . concurrently, the pwrt time-out (t pwrt ) is applied before the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm is applied. the total delay in this case is t fscm . refer to parameter sy35 in table 26-23 of section 26.0 electrical characteristics for specific t fscm values. the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit continues to oper- ate while in sleep or idle modes and resets the device should v dd fall below the bor threshold voltage. note: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to table 26-5 located in section 26.0 electrical characteris- tics for the full operating ranges of v dd and v cap . 2: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage = 1.8v when v dd v ddmin . v dd v cap v ss dspic33ep 3.3v c efc downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 286 ? 2013-2015 microchip technology inc. 23.6 watchdog timer (wdt) for dspic33epxxgs50x family devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 23.6.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a wdt time-out period (t wdt ), as shown in parameter sy12 in table 26-23 . a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler, time-out periods, ranges from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: on any device reset on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the noscx bits) or by hardware (i.e., fail-safe clock monitor) when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) when the device exits sleep or idle mode to resume normal operation by a clrwdt instruction during normal execution 23.6.2 sleep and idle modes if the wdt is enabled, it continues to run during sleep or idle modes. when the wdt time-out occurs, the device wakes and code execution continues from where the pwrsav instruction was executed. the corresponding sleep or idle bit (rcon<3:2>) needs to be cleared in software after the device wakes up. 23.6.3 enabling wdt the wdt is enabled or disabled by the wdten<1:0> configuration bits in the fwdt configuration register. when the wdten<1:0> configuration bits have been programmed to 0b11 , the wdt is always enabled. the wdt can be optionally controlled in software when the wdten<1:0> configuration bits have been programmed to 0b10 . the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disables the wdt during non-critical segments for maximum power savings. the wdt time-out flag bit, wdto (rcon<4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. 23.6.4 wdt window the watchdog timer has an optional windowed mode, enabled by programming the windis bit in the wdt configuration register (fwdt<7>). in the windowed mode (windis = 0 ), the wdt should be cleared based on the settings in the programmable watchdog timer window select bits (wdtwin<1:0>). figure 23-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide-by-n1) postscaler (divide-by-n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten wdten<1:0> lprc clock rs rs wake-up reset wdtwin<1:0> all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 287 dspic33epxxgs50x family 23.7 jtag interface the dspic33epxxgs50x family devices implement a jtag interface, which supports boundary scan device testing. detailed information on this interface is provided in future revisions of the document. 23.8 in-circuit serial programming? the dspic33epxxgs50x family devices can be seri- ally programmed while in the end application circuit. this is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the dspic33e/pic24e flash pr ogramming specification for devices with volatile configuration bits (ds70663) for details about in-circuit serial programming? (icsp?). any of the three pairs of programming clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 23.9 in-circuit debugger when mplab ? icd 3 or real ice? emulator is selected as a debugger, the in-circuit debugging function- ality is enabled. this function allows simple debugging functions when used with mplab ide. debugging func- tionality is controlled through the pgecx (emulation/ debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss and the pgecx/pgedx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins (pgecx and pgedx). 23.10 code protection and codeguard? security dspic33epxxgs50x devices offer multiple levels of security for protecting individual intellectual property. the program flash protection can be broken up into three segments: boot segment (bs), general segment (gs) and configuration segment (cs). boot segment has the highest security privilege and can be thought to have limited restrictions when accessing other segments. general segment has the least security and is intended for the end user system code. configuration segment contains only the device user configuration data which is located at the end of the program memory space. the code protection features are controlled by the configuration registers, fsec and fbslim. the fsec register controls the code-protect level for each segment and if that segment is write-protected. the size of bs and gs will depend on the bslim<12:0> setting and if the alternate interrupt vector table (aivt) is enabled. the bslim<12:0> bits define the number of pages for bs with each page containing 512 iw. the smallest bs size is one page, which will consist of the interrupt vector table (ivt) and 256 iw of code protection. if the aivt is enabled, the last page of bs will contain the aivt and will not contain any bs code. with aivt enabled, the smallest bs size is now two pages (1024 iw), with one page for the ivt and bs code, and the other page for the aivt. write protection of the bs does not cover the aivt. the last page of bs can always be programmed or erased by bs code. the general segment will start at the next page and will consume the rest of program flash except for the flash configuration words. the ivt will assume gs security only if bs is not enabled. the ivt is protected from being programmed or page erased when either security segment has enabled write protection. note: refer to programming and diagnostics (ds70608) in the dspic33/pic24 family reference manual for further information on usage, configuration and operation of the jtag interface. note: refer to codeguard? intermediate security (ds70005182) in the dspic33/ pic24 family reference manual for further information on usage, configuration and operation of codeguard security. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 288 ? 2013-2015 microchip technology inc. the different device security segments are shown in figure 23-3 . here, all three segments are shown but are not required. if only basic code protection is required, then gs can be enabled independently or combined with cs, if desired. figure 23-3: security segments example for dspic33ep64gs50x devices dspic33ep64gs50x family devices can be operated in dual partition mode, where security is required for each partition. when operating in dual partition mode, the active and inactive partitions both contain unique copies of the reset vector, interrupt vector tables (ivt and aivt, if enabled) and the flash configuration words. both partitions have the three security segments described previously. code may not be executed from the inactive partition, but it may be programmed by, and read from, the active partition, subject to defined code protection. figure 23-4 shows the different security segments for a device operating in dual partition mode. the device may also operate in a protected dual partition mode or in privileged dual partition mode. in protected dual partition mode, partition 1 is perma- nently erase/write-protected. this implementation allows for a factory default mode, which provides a fail-safe backup image to be stored in partition 1. for example, a fail-safe bootloader can be placed in partition 1, along with a fail-safe backup code image, which can be used or rewritten into partition 2 in the event of a failed flash update to partition 2. privileged dual partition mode performs the same function as protected dual partition mode, except additional constraints are applied in an effort to prevent code in the boot segment and general segment from being used against each other. figure 23-4: security segments example for dspic33ep64gs50x devices (dual partition modes) ivt and aivt assume ivt bs aivt + 256 iw (2) gs 0x000000 0x000200 bslim<12:0> 0x00b000 cs (1) note 1: if cs is write-protected, the last page (gs + cs) of program memory will be protected from an erase condition. 2: the last half (256 iw) of the last page of bs is unusable program memory. bs protection ivt bs aivt + 256iw (2) gs cs (1) unimplemented (read 0 s) ivt bs aivt + 256 iw (2) gs cs (1) note 1: if cs is write-protected, the last page (gs + cs) of program memory will be protected from an erase condition. 2: the last half (256 iw) of the last page of bs is unusable program memory. 0x0000000x000200 bslim<12:0> ivt and aivt assume ivt and aivt assume 0x0058000x400000 0x400200 bslim<12:0> 0x405800 bs protection bs protection downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 289 dspic33epxxgs50x family 24.0 instruction set summary the dspic33ep instruction set is almost identical to that of the dspic30f and dspic33f. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: word or byte-oriented operations bit-oriented operations literal operations dsp operations control operations table 24-1 lists the general symbols used in describing the instructions. the dspic33e instruction set summary in tab l e 2 4- 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: the first source operand, which is typically a register wb without any address modifier the second source operand, which is typically a register ws with or without an address modifier the destination of the result, which is typically a register wd with or without an address modifier however, word or byte-oriented file register instructions have two operands: the file register specified by the value f the destination, which could be either the file register f or the w0 register, which is denoted as wreg most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: the w register (with or without an address modifier) or file register (specified by the value of ws or f) the bit in the w register or file register (specified by a literal value or indirectly by the contents of register wb) the literal instructions that involve data movement can use some of the following operands: a literal value to be loaded into a w register or file register (specified by k) the w register or file register where the literal value is to be loaded (specified by wb or f) however, literal instructions that involve arithmetic or logical operations use some of the following operands: the first source operand, which is a register wb without any address modifier the second source operand, which is a literal value the destination of the result (only if not the same as the first source operand), which is typically a register wd with or without an address modifier the mac class of dsp instructions can use some of the following operands: the accumulator (a or b) to be used (required operand) the w registers to be used as the two operands the x and y address space prefetch operations the x and y address space prefetch destinations the accumulator write back destination the other dsp instructions do not involve any multiplication and can include: the accumulator to be used (required) the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier the amount of shift specified by a w register wn or a literal value the control instructions can use some of the following operands: a program memory address the mode of the table read and table write instructions note: this data sheet summarizes the features of the dspic33epxxgs50x family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the dspic33e/pic24e family reference manual , which is available from the microchip web site ( www.microchip.com ). downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 290 ? 2013-2015 microchip technology inc. most instructions are a single word. certain double-word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8msbs are 0 s. if this second word is executed as an instruction (by itself), it executes as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction, or a psv or table read is performed. in these cases, the execution takes multiple instruction cycles, with the additional instruction cycle(s) executed as a nop . certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the 16-bit mcu and dsc programmers reference manual (ds70157). table 24-1: symbols used in opcode descriptions field description #text means literal defined by text (text) means content of text [text] means the location addressed by text { } optional field or operation a ? {b, c, d} a is selected from the set of values b, c, d register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) acc one of two accumulators {a, b} awb accumulator write-back destination address register ?? {w13, [w13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ?? {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address ?? {0x0000...0x1fff} lit1 1-bit unsigned literal ?? {0,1} lit4 4-bit unsigned literal ?? {0...15} lit5 5-bit unsigned literal ?? {0...31} lit8 8-bit unsigned literal ?? {0...255} lit10 10-bit unsigned literal ?? {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal ?? {0...16384} lit16 16-bit unsigned literal ?? {0...65535} lit23 23-bit unsigned literal ?? {0...8388608}; lsb must be 0 none field does not require an entry, can be blank oa, ob, sa, sb dsp status bits: acca overflow, accb overflow, acca satu rate, accb saturate pc program counter slit10 10-bit signed literal ?? {-512...511} slit16 16-bit signed literal ?? {-32768...32767} slit6 6-bit signed literal ?? {-16...16} wb base w register ?? {w0...w15} wd destination w register ?? { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register ?? { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working register pair (direct addressing) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 291 dspic33epxxgs50x family wm*wm multiplicand and multiplier working r egister pair for square instructions ?? {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working r egister pair for dsp instructions ? {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers ?? {w0...w15} wnd one of 16 destination working registers ?? {w0...w15} wns one of 16 source working registers ?? {w0...w15} wreg w0 (working register used in file register instructions) ws source w register ?? { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register ?? { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions ? {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destination register for dsp instructions ?? {w4...w7} wy y data space prefetch address register for dsp instructions ? {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w1 1] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions ?? {w4...w7} table 24-1: symbols used in opcode descriptions (continued) field description downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 292 ? 2013-2015 microchip technology inc. table 24-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bootswp bootswp swap the active and inactive program flash space 12 n o n e 7 bra bra c,expr branch if carry 1 1 (4) none bra ge,expr branch if greater than or equal 1 1 (4) none bra geu,expr branch if unsigned greater than or equal 1 1 (4) none bra gt,expr branch if greater than 1 1 (4) none bra gtu,expr branch if unsigned greater than 1 1 (4) none bra le,expr branch if less than or equal 1 1 (4) none bra leu,expr branch if unsigned less than or equal 1 1 (4) none bra lt,expr branch if less than 1 1 (4) none bra ltu,expr branch if unsigned less than 1 1 (4) none bra n,expr branch if negative 1 1 (4) none bra nc,expr branch if not carry 1 1 (4) none bra nn,expr branch if not negative 1 1 (4) none bra nov,expr branch if not overflow 1 1 (4) none bra nz,expr branch if not zero 1 1 (4) none bra oa,expr branch if accumulator a overflow 1 1 (4) none bra ob,expr branch if accumulator b overflow 1 1 (4) none bra ov,expr branch if overflow 1 1 (4) none bra sa,expr branch if accumulator a saturated 1 1 (4) none bra sb,expr branch if accumulator b saturated 1 1 (4) none bra expr branch unconditionally 1 4 none bra z,expr branch if zero 1 1 (4) none bra wn computed branch 1 4 none 8 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 293 dspic33epxxgs50x family 9 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none 10 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 11 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 12 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 13 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 14 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 15 call call lit23 call subroutine 2 4 sfa call wn call indirect subroutine 1 4 sfa call.l wn call indirect subroutine (long address) 1 4 sfa 16 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clr acc,wx,wxd,wy,wyd,awb clear accumulator 1 1 oa,ob,sa,sb 17 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 18 com com f f = f 11 n , z com f,wreg wreg = f 11 n , z com ws,wd wd = ws 11 n , z 19 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit8 compare wb with lit8 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (wb C ws) 1 1 c,dc,n,ov,z 20 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 21 cpb cpb f compare f with wreg, with borrow 1 1 c,dc,n,ov,z cpb wb,#lit8 compare wb with lit8, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb C ws C c ) 1 1 c,dc,n,ov,z 22 cpseq cpseq wb,wn compare wb with wn, skip if = 1 1 (2 or 3) none cpbeq cpbeq wb,wn,expr compare wb with wn, branch if = 1 1 (5) none 23 cpsgt cpsgt wb,wn compare wb with wn, skip if > 1 1 (2 or 3) none cpbgt cpbgt wb,wn,expr compare wb with wn, branch if > 1 1 (5) none 24 cpslt cpslt wb,wn compare wb with wn, skip if < 1 1 (2 or 3) none cpblt cpblt wb,wn,expr compare wb with wn, branch if < 1 1 (5) none 25 cpsne cpsne wb,wn compare wb with wn, skip if ? 11 (2 or 3) none cpbne cpbne wb,wn,expr compare wb with wn, branch if ? 11 ( 5 ) n o n e table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 294 ? 2013-2015 microchip technology inc. 26 ctxtswp ctxtswp #1it3 switch cpu register context to context defined by lit3 12 n o n e ctxtswp wn switch cpu register context to context defined by wn 12 n o n e 27 daw daw wn wn = decimal adjust wn 1 1 c 28 dec dec f f = f C 1 1 1 c,dc,n,ov,z dec f,wreg wreg = f C 1 1 1 c,dc,n,ov,z dec ws,wd wd = ws C 1 1 1 c,dc,n,ov,z 29 dec2 dec2 f f = f C 2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f C 2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws C 2 1 1 c,dc,n,ov,z 30 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none 31 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 32 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 33 do do #lit15,expr do code to pc + expr, lit15 + 1 times 2 2 none do wn,expr do code to pc + expr, (wn) + 1 times 2 2 none 34 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 35 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 36 exch exch wns,wnd swap wns with wnd 1 1 none 37 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 38 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 39 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 40 goto goto expr go to address 2 4 none goto wn go to indirect 1 4 none goto.l wn go to indirect (long address) 1 4 none 41 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 42 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 43 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 44 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 45 lnk lnk #lit14 link frame pointer 1 1 sfa 46 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 47 mac mac wm*wn,acc,wx,wxd,wy,wyd,awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 295 dspic33epxxgs50x family 48 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 none mov f,wreg move f to wreg 1 1 none mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 12 n o n e mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 12 n o n e 49 movpag movpag #lit10,dsrpag move 10-bit literal to dsrpag 1 1 none movpag #lit8,tblpag move 8-bit literal to tblpag 1 1 none movpagw ws, dsrpag move ws<9:0> to dsrpag 1 1 none movpagw ws, tblpag move ws<7:0> to tblpag 1 1 none 50 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none 51 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 52 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd -(multiply wm by wn) to accumulator 1 1 none 53 msc msc wm*wm,acc,wx,wxd,wy,wyd,awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 54 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 11 n o n e mul.ss wb,ws,acc accumulator = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 11 n o n e mul.su wb,ws,acc accumulator = signed(wb) * unsigned(ws) 11 n o n e mul.su wb,#lit5,acc accumulator = signed(wb) * unsigned(lit5) 11 n o n e mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 11 n o n e mul.us wb,ws,acc accumulator = unsigned(wb) * signed(ws) 11 n o n e mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 11 n o n e mul.uu wb,#lit5,acc accumulator = unsigned(wb) * unsigned(lit5) 11 n o n e mul.uu wb,ws,acc accumulator = unsigned(wb) * unsigned(ws) 11 n o n e mulw.ss wb,ws,wnd wnd = signed(wb) * signed(ws) 1 1 none mulw.su wb,ws,wnd wnd = signed(wb) * unsigned(ws) 1 1 none mulw.us wb,ws,wnd wnd = unsigned(wb) * signed(ws) 1 1 none mulw.uu wb,ws,wnd wnd = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 11 n o n e mul.su wb,#lit5,wnd wnd = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 11 n o n e mul.uu wb,#lit5,wnd wnd = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 296 ? 2013-2015 microchip technology inc. 55 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 56 nop nop no operation 1 1 none nopr no operation 1 1 none 57 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 12 n o n e pop.s pop shadow registers 1 1 all 58 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 12 n o n e push.s push shadow registers 1 1 none 59 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 60 rcall rcall expr relative call 1 4 sfa rcall wn computed call 1 4 sfa 61 repeat repeat #lit15 repeat next instruction lit15 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 62 reset reset software device reset 1 1 none 63 retfie retfie return from interrupt 1 6 (5) sfa 64 retlw retlw #lit10,wn return with literal in wn 1 6 (5) sfa 65 return return return from subroutine 1 6 (5) sfa 66 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 67 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 68 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z 69 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 70 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 71 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 72 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 73 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 297 dspic33epxxgs50x family 74 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 75 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f C wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f C wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn C lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb C ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb C lit5 1 1 c,dc,n,ov,z 76 subb subb f f = f C wreg C (c )1 1 c , d c , n , o v , z subb f,wreg wreg = f C wreg C (c )1 1 c , d c , n , o v , z subb #lit10,wn wn = wn C lit10 C (c )1 1 c , d c , n , o v , z subb wb,ws,wd wd = wb C ws C (c )1 1 c , d c , n , o v , z subb wb,#lit5,wd wd = wb C lit5 C (c )1 1 c , d c , n , o v , z 77 subr subr f f = wreg C f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg C f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws C wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 C wb 1 1 c,dc,n,ov,z 78 subbr subbr f f = wreg C f C (c )1 1 c , d c , n , o v , z subbr f,wreg wreg = wreg C f C (c )1 1 c , d c , n , o v , z subbr wb,ws,wd wd = ws C wb C (c )1 1 c , d c , n , o v , z subbr wb,#lit5,wd wd = lit5 C wb C (c )1 1 c , d c , n , o v , z 79 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 80 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 5 none 81 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 5 none 82 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 83 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 84 ulnk ulnk unlink frame pointer 1 1 sfa 85 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 86 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles ( 1 ) status flags affected note 1: read and read-modify-write (e.g., bit operations and logical operation s) on non-cpu sfrs incur an additional instruction cycle. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 298 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 299 dspic33epxxgs50x family 25.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 25.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 300 ? 2013-2015 microchip technology inc. 25.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16 and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 25.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline assembly code conditional assembly for multipurpose source files directives that allow complete control over the assembly process 25.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 301 dspic33epxxgs50x family 25.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 25.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 25.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 25.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the target via a microchip debug (rj-11) connector (com- patible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 25.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 302 ? 2013-2015 microchip technology inc. 25.11 demonstration/development boards, evaluation kits and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 25.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 303 dspic33epxxgs50x family 26.0 electrical characteristics this section provides an overview of the dspic33epxxgs50x fa mily electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the dspic33epxxgs50x family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss ( 3 ) ..................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 3.0v ( 3 ) ................................................... -0.3v to +5.5v voltage on any 5v tolerant pin with respect to vss when v dd < 3.0v ( 3 ) ................................................... -0.3v to +3.6v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ( 2 ) ...........................................................................................................................300 ma maximum current sunk/sourced by any 4x i/o pin................................................................................. .................15 ma maximum current sunk/sourced by any 8x i/o pin ................................................................................. .................25 ma maximum current sunk by all ports ( 2 ) ....................................................................................................................200 ma note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those, or any other conditions above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 6- 2 ). 3: see the pin diagrams section for the 5v tolerant pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 304 ? 2013-2015 microchip technology inc. 26.1 dc characteristics table 26-1: operating mips vs. voltage characteristic v dd range (in volts) temperature range (in c) maximum mips dspic33epxxgs50x family 3.0v to 3.6v ( 1 ) -40c to +85c 70 3.0v to 3.6v ( 1 ) -40c to +125c 60 note 1: device is functional at v bormin < v dd < v ddmin . analog modules (adc, pgas and comparators) may have degraded performance. device functionality is tested but not characterized. refer to parameter bo10 in table 26-13 for the minimum and maximum bor values. table 26-2: thermal operating conditions rating symbol min. typ. max. unit industrial temperature devices operating junction temperature range t j -40 +125 c operating ambient temperature range t a -40 +85 c extended temperature devices operating junction temperature range t j -40 +140 c operating ambient temperature range t a -40 +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd C ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ? ({v dd C v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j C t a )/ ? ja w table 26-3: thermal packaging characteristics characteristic symbol typ. max. unit notes package thermal resistance, 64-pin tqfp 10x10x1 mm ? ja 49.0 c/w 1 package thermal resistance, 48-pin tqfp 7x7x1.0 mm ? ja tbd c/w 1 package thermal resistance, 44-pin qfn 8x8 mm ? ja 29.0 c/w 1 package thermal resistance, 44-pin tqfp 10x10x1 mm ? ja 50.0 c/w 1 package thermal resistance, 28-pin qfn-s 6x6x0.9 mm ? ja 30.0 c/w 1 package thermal resistance, 28-pin uqfn 6x6x0.5 mm ? ja 26.0 c/w 1 package thermal resistance, 28-pin soic 7.50 mm ? ja 70.0 c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 305 dspic33epxxgs50x family table 26-5: filter capacitor (c efc ) specifications table 26-4: dc temperature and voltage specifications dc characteristics standard operating conditions (see note 1 ): 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions operating voltage dc10 v dd supply voltage 3.0 3.6 v dc12 v dr ram retention voltage 1.8 v ( note 2 ) dc16 v por v dd start voltage to ensure internal power-on reset signal v ss v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 1.0 v/ms 0v-3v in 3 ms note 1: device is functional at v bormin < v dd < v ddmin . analog modules (adc, pgas and comparators) may have degraded performance. device functionality is tested but not characterized. refer to parameter bo10 in table 26-13 for the minimum and maximum bor values. 2: this is the limit to which v dd may be lowered and the ram contents will always be retained. standard operating conditions (unless otherwise stated): operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min. typ. max. units comments c efc external filter capacitor value ( 1 ) 4.7 10 ? f capacitor must have a low series resistance (<1 ohm) note 1: typical v cap voltage = 1.8 volts when v dd ? v ddmin . downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 306 ? 2013-2015 microchip technology inc. table 26-6: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typ. max. units conditions operating current (i dd ) ( 1 ) dc20d 7 12 ma -40c 3.3v 10 mips dc20a 7 12 ma +25c dc20b 7 12 ma +85c dc20c 7 12 ma +125c dc22d 11 19 ma -40c 3.3v 20 mips dc22a 11 19 ma +25c dc22b 11 19 ma +85c dc22c 11 19 ma +125c dc24d 19 30 ma -40c 3.3v 40 mips dc24a 19 30 ma +25c dc24b 19 30 ma +85c dc24c 19 30 ma +125c dc25d 26 41 ma -40c 3.3v 60 mips dc25a 26 41 ma +25c dc25b 26 41 ma +85c dc25c 26 41 ma +125c dc26d 30 46 ma -40c 3.3v 70 mips dc26a 30 46 ma +25c dc26b 30 46 ma +85c dc27d 51 81 ma -40c 3.3v 70 mips ( note 2 ) dc27a 51 81 ma +25c dc27b 52 82 ma +85c dc27c 53 83 ma +125c note 1: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: oscillator is configured in ec mode with pll, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating or being clocked (all defined pmdx bits are set) cpu is executing while(1) statement jtag is disabled 2: for this specification, the following test conditions apply: apll clock is enabled all 5 pwms enabled and operating at maximum speed (ptcon2<2:0> = 000 ), ptper = 1000h, 50% duty cycle all other peripherals are disabled (corresponding pmdx bits are set) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 307 dspic33epxxgs50x family table 26-7: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typ. max. units conditions idle current (i idle ) ( 1 ) dc40d 2 4 ma -40c 3.3v 10 mips dc40a 2 4 ma +25c dc40b 2 4 ma +85c dc40c 2 4 ma +125c dc42d 3 6 ma -40c 3.3v 20 mips dc42a 3 6 ma +25c dc42b 3 6 ma +85c dc42c 3 6 ma +125c dc44d 6 12 ma -40c 3.3v 40 mips dc44a 6 12 ma +25c 12 dc44b 6 ma +85c 12 dc44c 6 ma +125c dc45d 8 15 ma -40c 3.3v 60 mips dc45a 8 15 ma +25c 15 dc45b 8 ma +85c 15 dc45c 8 ma +125c dc46d 10 20 ma -40c 3.3v 70 mips dc46a 10 20 ma +25c 20 dc46b 10 ma +85c note 1: base idle current (i idle ) is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock is active; osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled no peripheral modules are operating or being clocked (all defined pmdx bits are set) the nvmsidl bit (nvmcon<12>) = 1 (i.e., flash regulator is set to standby while the device is in idle mode) the vregsf bit (rcon<11>) = 0 (i.e., flash regulator is set to standby while the device is in sleep mode) jtag is disabled downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 308 ? 2013-2015 microchip technology inc. table 26-8: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typ. max. units conditions power-down current (i pd ) ( 1 ) dc60d 12 100 ? a -40c 3.3v dc60a 18 100 ? a+ 2 5 c dc60b 130 400 ? a+ 8 5 c dc60c 500 1100 ? a +125c note 1: i pd (sleep) current is measured as follows: cpu core is off, oscillator is configured in ec mode and external clock is active; osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled all peripheral modules are disabled (pmdx bits are all set) the vregs bit (rcon<8>) = 0 (i.e., core regulator is set to standby while the device is in sleep mode) the vregsf bit (rcon<11>) = 0 (i.e., flash regulator is set to standby while the device is in sleep mode) jtag is disabled table 26-9: dc characteristics: watchdog timer delta current ( ? i wdt ) ( 1 ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typ. max. units conditions dc61d 13 50 ? a- 4 0 c 3.3v dc61a 19 80 ? a +25c dc61b 12 ? a +85c dc61c 13 ? a +125c note 1: the ? i wdt current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. all parameters are characterized but not tested during manufacturing. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 309 dspic33epxxgs50x family table 26-10: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typ. max. doze ratio units conditions doze current (i doze ) ( 1 ) dc73a ( 2 ) 20 40 1:2 ma -40c 3.3v f osc = 140 mhz dc73g 9 20 1:128 ma dc70a ( 2 ) 20 40 1:2 ma +25c 3.3v f osc = 140 mhz dc70g 9 20 1:128 ma dc71a ( 2 ) 20 40 1:2 ma +85c 3.3v f osc = 140 mhz dc71g 9 20 1:128 ma dc72a ( 2 ) 20 40 1:2 ma +125c 3.3v f osc = 120 mhz dc72g 9 20 1:128 ma note 1: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i doze measurements are as follows: oscillator is configured in ec mode and external clock is active, osc 1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating or being clocked (all defined pmdx bits are set) cpu is executing while(1) statement jtag is disabled 2: these parameter are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 310 ? 2013-2015 microchip technology inc. table 26-11: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions v il input low voltage di10 any i/o pin and mclr v ss 0 . 2 v dd v di18 i/o pins with sdax, sclx v ss 0.3 v dd v smbus disabled di19 i/o pins with sdax, sclx v ss 0.8 v smbus enabled v ih input high voltage di20 i/o pins not 5v tolerant ( 4 ) 0.8 v dd v dd v i/o pins 5v tolerant and mclr ( 4 ) 0.8 v dd 5 . 5v 5v tolerant i/o pins with sdax, sclx ( 4 ) 0.8 v dd 5.5 v smbus disabled 5v tolerant i/o pins with sdax, sclx ( 4 ) 2.1 5.5 v smbus enabled i/o pins with sdax, sclx not 5v tolerant ( 4 ) 0.8 v dd v dd v smbus disabled i/o pins with sdax, sclx not 5v tolerant ( 4 ) 2.1 v dd v smbus enabled di30 i cnpu input change notification pull-up current 150 340 550 ? av dd = 3.3v, v pin = v ss di31 i cnpd input change notification pull-down current ( 5 ) 20 60 100 ? av dd = 3.3v, v pin = v dd note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: v ih source > (v dd + 0.3) for pins that are not 5v tolerant only. 7: digital 5v tolerant pins do not have internal high-side diodes to v dd and cannot tolerate any positive input injection current. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted provided the mathematical absolute instantaneous sum of the input injection curr ents from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 311 dspic33epxxgs50x family i il input leakage current ( 2 , 3 ) di50 i/o pins 5v tolerant ( 4 ) -1 +1 ? av ss ? v pin ? v dd , pin at high-impedance di51 i/o pins not 5v tolerant ( 4 ) -1 +1 ? av ss ? v pin ? v dd , pin at high-impedance, -40c ? t a ? +85c di51a i/o pins not 5v tolerant ( 4 ) -1 +1 ? a analog pins shared with external reference pins, -40c ? t a ? +85c di51b i/o pins not 5v tolerant ( 4 ) -1 +1 ? av ss ? v pin ? v dd , pin at high-impedance, -40c ? t a ? +125c di51c i/o pins not 5v tolerant ( 4 ) -1 +1 ? a analog pins shared with external reference pins, -40c ? t a ? +125c di55 mclr -5 +5 ? av ss ?? v pin ?? v dd di56 osc1 -5 +5 ? av ss ?? v pin ?? v dd , xt and hs modes table 26-11: dc characteristics: i/o pin input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: v ih source > (v dd + 0.3) for pins that are not 5v tolerant only. 7: digital 5v tolerant pins do not have internal high-side diodes to v dd and cannot tolerate any positive input injection current. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted provided the mathematical absolute instantaneous sum of the input injection curre nts from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 312 ? 2013-2015 microchip technology inc. i icl input low injection current di60a 0 -5 ( 5 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap and rb7 i ich input high injection current di60b 0 +5 ( 6 , 7 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb7 and all 5v tolerant pins ( 7 ) ? i ict total input injection current di60c (sum of all i/o and control pins) -20 ( 9 ) + 2 0 ( 9 ) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl | + | i ich |) ? ? i ict table 26-11: dc characteristics: i/o pin input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: v ih source > (v dd + 0.3) for pins that are not 5v tolerant only. 7: digital 5v tolerant pins do not have internal high-side diodes to v dd and cannot tolerate any positive input injection current. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted provided the mathematical absolute instantaneous sum of the input injection curr ents from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 313 dspic33epxxgs50x family table 26-12: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. symbol characteristic min. typ. max. units conditions do10 v ol output low voltage 4x sink driver pins ( 2 ) 0 . 4vv dd = 3.3v, i ol ? 6 ma, -40c ? t a ? +85c, i ol ? 5 ma, +85c ? t a ? +125c output low voltage 8x sink driver pins ( 3 ) 0 . 4vv dd = 3.3v, i ol ? 12 ma, -40c ? t a ? +85c, i ol ? 8 ma, +85c ? t a ? +125c do20 v oh output high voltage 4x source driver pins ( 2 ) 2.4 v i oh ? -10 ma, v dd = 3.3v output high voltage 8x source driver pins ( 3 ) 2.4 v i oh ? -15 ma, v dd = 3.3v do20a v oh 1 output high voltage 4x source driver pins ( 2 ) 1.5 ( 1 ) v i oh ? -14 ma, v dd = 3.3v 2.0 ( 1 ) i oh ? -12 ma, v dd = 3.3v 3.0 ( 1 ) i oh ? -7 ma, v dd = 3.3v output high voltage 8x source driver pins ( 3 ) 1.5 ( 1 ) v i oh ? -22 ma, v dd = 3.3v 2.0 ( 1 ) i oh ? -18 ma, v dd = 3.3v 3.0 ( 1 ) i oh ? -10 ma, v dd = 3.3v note 1: parameters are characterized but not tested. 2: includes ra0-ra2, rb0-rb1, rb9-rb10, rc1-rc2, rc9-rc10, rc12 and rd7 pins. 3: includes all i/o pins that are not 4x driver pins (see note 2 ). table 26-13: electrical characteristics: bor dc characteristics standard operating conditions (see note 1 ): 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. ( 2 ) typ. max. units conditions bo10 v bor bor event on v dd transition high-to-low 2.65 2.95 v v dd ( notes 2 and 3 ) note 1: device is functional at v bormin < v dd < v ddmin , but will have degraded performance. device functionality is tested, but not characterized. analog modules (adc, pgas and comparators) may have degraded performance. 2: parameters are for design guidance only and are not tested in manufacturing. 3: the v bor specification is relative to v dd . downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 314 ? 2013-2015 microchip technology inc. table 26-14: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions program flash memory d130 e p cell endurance 10,000 e/w -40 ? c to +125 ? c d131 v pr v dd for read 3.0 3.6 v d132b v pew v dd for self-timed write 3.0 3.6 v d134 t retd characteristic retention 20 year provided no other specifications are violated, -40 ? c to +125 ? c d135 i ddp supply current during programming ( 2 ) 1 0 m a d136 i peak instantaneous peak current during start-up 1 5 0m a d137a t pe page erase time 19.7 20.1 ms t pe = 146893 frc cycles, t a = +85c ( note 3 ) d137b t pe page erase time 19.5 20.3 ms t pe = 146893 frc cycles, t a = +125c ( note 3 ) d138a t ww word write cycle time 46.5 47.3 s t ww = 346 frc cycles, t a = +85c ( note 3 ) d138b t ww word write cycle time 46.0 47.9 s t ww = 346 frc cycles, t a = +125c ( note 3 ) d139a t rw row write time 667 679 s t rw = 4965 frc cycles, t a = +85c ( note 3 ) d139b t rw row write time 660 687 s t rw = 4965 frc cycles, t a = +125c ( note 3 ) note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. 2: parameter characterized but not tested in manufacturing. 3: other conditions: frc = 7.37 mhz, tun<5:0> = 011111 (for minimum), tun<5:0> = 100000 (for maximum). this parameter depends on the frc accuracy (see table 26-20 ) and the value of the frc oscillator tuning register (see register 8-4 ). for complete details on calculating the minimum and maximum time, see section 5.3 programming operations . downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 315 dspic33epxxgs50x family 26.2 ac characteristics and timing parameters this section defines the dspic33epxxgs50x family ac characteristics and timing parameters. table 26-15: temperature and vo ltage specifications C ac figure 26-1: load conditions for device timing specifications table 26-16: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended operating voltage v dd range as described in section 26.1 dc characteristics . param no. symbol characteristic min. typ. max. units conditions do50 c osco osc2 pin 15 pf in xt and hs modes, when external clock is used to drive osc1 do56 c io all i/o pins and osc2 50 pf ec mode do58 c b sclx, sdax 400 pf in i 2 c mode v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 C for all pins except osc2 load condition 2 C for osc2 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 316 ? 2013-2015 microchip technology inc. figure 26-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 os20 os30 os30 os40 os41 os31 os25 os31 q4 table 26-17: external clo ck timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symb characteristic min. typ. ( 1 ) max. units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc 60 mhz ec oscillator crystal frequency 3.5 10 1040 mhzmhz xths os20 t osc t osc = 1/f osc 8.33 dc ns +125c t osc = 1/f osc 7.14 dc ns +85c os25 t cy instruction cycle time ( 2 ) 16.67 dc ns +125c instruction cycle time ( 2 ) 14.28 dc ns +85c os30 tosl, to s h external clock in (osc1) high or low time 0.45 x t osc 0.55 x t osc ns ec os31 tosr, to s f external clock in (osc1) rise or fall time 20 ns ec os40 tckr clko rise time ( 3 , 4 ) 5 . 2n s os41 tckf clko fall time ( 3 , 4 ) 5 . 2n s os42 g m external oscillator transconductance ( 4 ) 12 ma/v hs, v dd = 3.3v, t a = +25c 6m a / v x t , v dd = 3.3v, t a = +25c note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type, under standard operating condition s, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at minimum values with an external clock applied to the osc1 pin. when an external clock input is used, the maximum cycle time limit is dc (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. 4: this parameter is characterized but not tested in manufacturing. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 317 dspic33epxxgs50x family table 26-18: pll clock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 0.8 8.0 mhz ecpll, xtpll modes os51 f vco on-chip vco system frequency 120 340 mhz os52 t lock pll start-up time (lock time) 0.9 1.5 3.1 ms os53 d clk clko stability (jitter) ( 2 ) -3 0.5 3 % note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this jitter specification is based on clock cycle-by-clock cycle measurements. to get the effectiv e jitter for individual time bases, or communication clocks used by the application, use the following formula: for example, if f osc = 120 mhz and the spix bit rate = 10 mhz, the effective jitter is as follows: effective jitter d clk f osc time base or communication clock -------------------------------------------------------------------------------------- - ------------------------------------------------------------------------------------------- = effective jitter d clk 120 10 -------- - ------------- - d clk 12 ------------- - d clk 3.464 ------------- - === table 26-19: auxiliary pll cl ock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions os56 f hpout on-chip 16x pll cco frequency 112 118 120 mhz os57 f hpin on-chip 16x pll phase detector input frequency 7.0 7.37 7.5 mhz os58 t su frequency generator lock time 1 0 s note 1: data in typ column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 318 ? 2013-2015 microchip technology inc. table 26-20: internal frc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min. typ. max. units conditions internal frc accuracy @ frc frequency = 7.37 mhz ( 1 ) f20a frc -2 0.5 +2 % -40c ? t a ?? -10c v dd = 3.0-3.6v -0.9 0.5 +0.9 % -10c ? t a ?? +85c v dd = 3.0-3.6v f20b frc -2 1 +2 % +85c ? t a ? +125c v dd = 3.0-3.6v note 1: frequency is calibrated at +25c and 3.3v. tunx bits can be used to compensate for temperature drift. table 26-21: internal lprc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min. typ. max. units conditions lprc @ 32.768 khz ( 1 ) f21a lprc -30 +30 % -40c ? t a ? -10c v dd = 3.0-3.6v -20 +20 % -10c ? t a ? +85c v dd = 3.0-3.6v f21b lprc -30 +30 % +85c ? t a ? +125c v dd = 3.0-3.6v note 1: this is the change of the lprc frequency as v dd changes. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 319 dspic33epxxgs50x family figure 26-3: i/o timing characteristics figure 26-4: bor and master cle ar reset timing characteristics note: refer to figure 26-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 26-22: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. ( 1 ) max. units conditions do31 t io r port output rise time 5 10 ns do32 t io f port output fall time 5 10 ns di35 t inp intx pin high or low time (input) 20 ns di40 t rbp cnx high or low time (input) 2 t cy note 1: data in typ. column is at 3.3v, +25c unless otherwise stated. mclr (sy20) bor (sy30) t mclr t bor reset sequence cpu starts fetching code various delays (depending on configuration) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 320 ? 2013-2015 microchip technology inc. table 26-23: reset, watchdog timer, oscill ator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sy00 t pu power-up period 400 600 ? s sy10 t ost oscillator start-up time 1024 t osc t osc = osc1 period sy12 t wdt watchdog timer time-out period 0.81 1.22 ms wdtpre = 0 , wdtpost<3:0> = 0000 , using lprc tolerances indicated in f21 (see table 26-21 ) at +85c 3.25 4.88 ms wdtpre = 1 , wdtpost<3:0> = 0000 , using lprc tolerances indicated in f21 (see table 26-21 ) at +85c sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset 0.68 0.72 1.2 ? s sy20 t mclr mclr pulse width (low) 2 ? s sy30 t bor bor pulse width (low) 1 ? s sy35 t fscm fail-safe clock monitor delay 500 900 ? s -40c to +85c sy36 t vreg voltage regulator standby-to-active mode transition time 3 0 ? s sy37 t oscdfrc frc oscillator start-up delay 4 8 ? s sy38 t oscdlprc lprc oscillator start-up delay 7 0 ? s note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 321 dspic33epxxgs50x family figure 26-5: timer1-timer5 externa l clock timing characteristics note: refer to figure 26-1 for load conditions. os60 txck tmrx tx10 tx11 tx15 tx20 table 26-24: timer1 external clock timing requirements ( 1 ) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 2 ) min. typ. max. units conditions ta10 t tx h t1ck high time synchronous mode greater of: 20 or (t cy + 20)/n ns must also meet parameter ta15, n = prescale value (1, 8, 64, 256) asynchronous 35 ns ta11 t tx lt 1 c k l o w time synchronous mode greater of: 20 or (t cy + 20)/n ns must also meet parameter ta15, n = prescale value (1, 8, 64, 256) asynchronous 10 ns ta15 t tx p t1ck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ns n = prescale value (1, 8, 64, 256) os60 ft1 t1ck oscillator input frequency range (oscillator enabled by setting bit, tcs (t1con<1>)) dc 50 khz ta20 t ckextmrl delay from external t1ck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 ns note 1: timer1 is a type a timer. 2: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 322 ? 2013-2015 microchip technology inc. table 26-25: timer2 and timer4 (type b timer) external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. max. units conditions tb10 ttxh txck high time synchronous mode greater of: 20 or (t cy + 20)/n ns must also meet parameter tb15, n = prescale value (1, 8, 64, 256) tb11 ttxl txck low time synchronous mode greater of: 20 or (t cy + 20)/n ns must also meet parameter tb15, n = prescale value (1, 8, 64, 256) tb15 ttxp txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 ns note 1: these parameters are characterized but not tested in manufacturing. table 26-26: timer3 and timer5 (type c timer) external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. max. units conditions tc10 ttxh txck high time synchronous t cy + 20 ns must also meet parameter tc15 tc11 ttxl txck low time synchronous t cy + 20 ns must also meet parameter tc15 tc15 ttxp txck input period synchronous with prescaler 2 t cy + 40 ns n = prescale value (1, 8, 64, 256) tc20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 323 dspic33epxxgs50x family figure 26-6: input capture x (icx) timing characteristics icx ic10 ic11 ic15 note: refer to figure 26-1 for load conditions. table 26-27: input capture x module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. symbol characteristics ( 1 ) min. max. units conditions ic10 t cc l icx input low time greater of: 12.5 + 25 or (0.5 t cy /n) + 25 ns must also meet parameter ic15 n = prescale value (1, 4, 16) ic11 t cc h icx input high time greater of: 12.5 + 25 or (0.5 t cy /n) + 25 ns must also meet parameter ic15 ic15 t cc p icx input period greater of: 25 + 50 or (1 t cy /n) + 50 n s note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 324 ? 2013-2015 microchip technology inc. figure 26-7: output compare x mo dule (ocx) timing characteristics figure 26-8: ocx/pwmx module timing characteristics ocx oc11 oc10 (output compare note: refer to figure 26-1 for load conditions. or pwm mode) table 26-28: output compare x module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. max. units conditions oc10 tccf ocx output fall time ns see parameter do32 oc11 tccr ocx output rise time ns see parameter do31 note 1: these parameters are characterized but not tested in manufacturing. ocfa ocx oc20 oc15 table 26-29: ocx/pwmx module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. max. units conditions oc15 t fd fault input to pwmx i/o change t cy + 20 ns oc20 t flt fault input pulse width t cy + 20 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 325 dspic33epxxgs50x family figure 26-9: high-speed pwmx mo dule fault timing characteristics figure 26-10: high-speed pwmx module timing characteristics fault input pwmx mp30 mp20 (active-low) pwmx mp11 mp10 note: refer to figure 26-1 for load conditions. table 26-30: high-speed pwmx module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. max. units conditions mp10 t fpwm pwmx output fall time ns see parameter do32 mp11 t rpwm pwmx output rise time ns see parameter do31 mp20 t fd fault input ? to pwmx i/o change 1 5n s mp30 t fh fault input pulse width 15 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 326 ? 2013-2015 microchip technology inc. table 26-31: spix maximu m data/clock rate summary figure 26-11: spix master mode (half-duplex, transmit only, cke = 0 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 26-31 0 , 10 , 10 , 1 9 mhz table 26-32 10 , 11 9 mhz table 26-33 00 , 11 15 mhz table 26-34 100 11 mhz table 26-35 110 15 mhz table 26-36 010 11 mhz table 26-37 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 327 dspic33epxxgs50x family figure 26-12: spix master mode ( half-duplex, transmit only, cke = 1 ) timing characteristics table 26-32: spix master mode (half-duplex, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp10 fscp maximum sckx frequency 15 mhz ( note 3 ) sp20 tscf sckx output fall time ns see parameter do32 ( note 4 ) sp21 tscr sckx output rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp10 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 328 ? 2013-2015 microchip technology inc. figure 26-13: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 26-33: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp10 fscp maximum sckx frequency 9 mhz ( note 3 ) sp20 tscf sckx output fall time ns see parameter do32 ( note 4 ) sp21 tscr sckx output rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp41 lsb in bit 14 - - - -1 sdix sp40 sp10 msb in downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 329 dspic33epxxgs50x family figure 26-14: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 26-34: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp10 fscp maximum sckx frequency 9 mhz -40c to +125c ( note 3 ) sp20 tscf sckx output fall time ns see parameter do32 ( note 4 ) sp21 tscr sckx output rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 3 0 n s sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 3 0 n s sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 3 0 n s note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp10 msb in note: refer to figure 26-1 for load conditions. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 330 ? 2013-2015 microchip technology inc. figure 26-15: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp60 sdix sp30, sp31 msb bit 14 - - - - - -1 lsb sp51 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp40 sp41 note: refer to figure 26-1 for load conditions. sp36 sp50 sp70 sp35 msb in downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 331 dspic33epxxgs50x family table 26-35: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp70 fscp maximum sckx input frequency lesser of: f p or 15 mhz ( note 3 ) sp72 tscf sckx input fall time ns see parameter do32 ( note 4 ) sp73 tscr sckx input rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx ?? input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns ( note 4 ) sp52 tsch2ssh, tscl2ssh ssx ?? after sckx edge 1.5 t cy + 40 ns ( note 4 ) sp60 tssl2dov sdox data output valid after ssx edge 50 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 332 ? 2013-2015 microchip technology inc. figure 26-16: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp60 sdix sp30, sp31 msb bit 14 - - - - - -1 lsb sp51 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 26-1 for load conditions. sp36 sp50 sp35 msb in downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 333 dspic33epxxgs50x family table 26-36: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp70 fscp maximum sckx input frequency lesser of: f p or 11 mhz ( note 3 ) sp72 tscf sckx input fall time ns see parameter do32 ( note 4 ) sp73 tscr sckx input rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx ?? input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns ( note 4 ) sp52 tsch2ssh, tscl2ssh ssx ?? after sckx edge 1.5 t cy + 40 ns ( note 4 ) sp60 tssl2dov sdox data output valid after ssx edge 50 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 334 ? 2013-2015 microchip technology inc. figure 26-17: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp50 sp40 sp41 sp30, sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 note: refer to figure 26-1 for load conditions. sdix sp70 sp36 msb in downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 335 dspic33epxxgs50x family table 26-37: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp70 fscp maximum sckx input frequency 15 mhz ( note 3 ) sp72 tscf sckx input fall time ns see parameter do32 ( note 4 ) sp73 tscr sckx input rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx ?? input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns ( note 4 ) sp52 tsch2ssh, tscl2ssh ssx ?? after sckx edge 1.5 t cy + 40 ns ( note 4 ) note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 336 ? 2013-2015 microchip technology inc. figure 26-18: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp50 sp40 sp41 sp30, sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sdix sp70 sp36 msb in note: refer to figure 26-1 for load conditions. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 337 dspic33epxxgs50x family table 26-38: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions sp70 fscp maximum sckx input frequency 11 mhz ( note 3 ) sp72 tscf sckx input fall time ns see parameter do32 ( note 4 ) sp73 tscr sckx input rise time ns see parameter do31 ( note 4 ) sp30 tdof sdox data output fall time ns see parameter do32 ( note 4 ) sp31 tdor sdox data output rise time ns see parameter do31 ( note 4 ) sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx ?? input 120 ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 50 ns ( note 4 ) sp52 tsch2ssh, tscl2ssh ssx ?? after sckx edge 1.5 t cy + 40 ns ( note 4 ) note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 338 ? 2013-2015 microchip technology inc. figure 26-19: i2cx bus start/stop bits timing characteristics (master mode) figure 26-20: i2cx bus data timing characteristics (master mode) sclxsdax start condition stop condition note: refer to figure 26-1 for load conditions. im31 im30 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 26-1 for load conditions. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 339 dspic33epxxgs50x family table 26-39: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 4 ) min. ( 1 ) max. units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 2) ? s 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 2) ? s 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) 300 ns im25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ( 2 ) 40 ns im26 t hd : dat data input hold time 100 khz mode 0 ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 2 ) 0.2 ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 2) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 2) ? s after this period, the first clock pulse is generated 400 khz mode t cy /2 (brg +2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 2) ? s 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im34 t hd : sto stop condition hold time 100 khz mode t cy /2 (brg + 2) ? s 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode ( 2 ) t cy /2 (brg + 2) ? s im40 t aa : scl output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode ( 2 ) 400 ns im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode ( 2 ) 0.5 ? s im50 c b bus capacitive loading 400 pf im51 t pgd pulse gobbler delay 65 390 ns ( note 3 ) note 1: brg is the value of the i 2 c baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: typical value for this parameter is 130 ns. 4: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 340 ? 2013-2015 microchip technology inc. figure 26-21: i2cx bus start/stop bits timing characteristics (slave mode) figure 26-22: i2cx bus data timi ng characteristics (slave mode) sclxsdax start condition stop condition is30 is31 is34 is33 is30 is31 is33 is11 is10 is20 is25 is40 is40 is45 is21 sclx sdax in sdax out is26 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 341 dspic33epxxgs50x family table 26-40: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 3 ) min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s 400 khz mode 1.3 ? s 1 mhz mode ( 1 ) 0.5 ? s is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode ( 1 ) 0.5 ? s is20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) 1 0 0n s is21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) 3 0 0n s is25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ( 1 ) 100 ns is26 t hd : dat data input hold time 100 khz mode 0 ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 1 ) 00 . 3 ? s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.6 ? s is34 t hd : sto stop condition hold time 100 khz mode 4 ? s 400 khz mode 0.6 ? s 1 mhz mode ( 1 ) 0.25 ? s is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode ( 1 ) 03 5 0n s is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode ( 1 ) 0.5 ? s is50 c b bus capacitive loading 400 pf is51 t pgd pulse gobbler delay 65 390 ns ( note 2 ) note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 2: typical value for this parameter is 130 ns. 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 342 ? 2013-2015 microchip technology inc. figure 26-23: uart x module i/o timing characteristics table 26-41: uartx module i/o timing requirements table 26-42: analog curre nt specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions ua10 t uabaud uartx baud time 66.67 ns ua11 f baud uartx baud frequency 15 mbps ua20 t cwf start bit pulse width to trigger uartx wake-up 500 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. symbol characteristic ( 1 ) min. typ. ( 2 ) max. units conditions avd01 i dd analog modules current consumption 9 ma characterized data with the following modules enabled: apll, 5 adc cores, 2 pgas and 4 analog comparators note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ. column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. ua20 uxrx msb in lsb in bit 6-1 ua10 u x tx downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 343 dspic33epxxgs50x family table 26-43: adc mo dule specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) ( 5 ) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of: v dd C 0.3 or 3.0 lesser of: v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss v ss + 0.3 v reference inputs ad06 v refl reference voltage low av ss v ( note 1 ) ad07 v ref absolute reference voltage (v refh C v refl ) 2.7 av dd v ( note 3 ) ad08 i ref reference input current 5 10 ? a adc operating or in standby analog input ad12 v inh -v inl full-scale input span av ss a v dd v ad14 v in absolute input voltage av ss C 0.3 av dd + 0.3 v ad17 r in recommended impedance of analog voltage source 1 0 0 ? for minimum sampling time ( note 1 ) ad66 v bg internal voltage reference source 1 . 2v adc accuracy: pseudo-differential input ad20a nr resolution 12 bits ad21a inl integral nonlinearity > -3 < 3 lsb av ss = 0v, av dd = 3.3v ad22a dnl differential nonlinearity > -1 < 1 lsb av ss = 0v, av dd = 3.3v ( note 2 ) ad23a g err gain error (dedicated core) > 5 13 < 20 lsb av ss = 0v, av dd = 3.3v gain error (shared core) > -1 5 < 10 lsb ad24a e off offset error (dedicated core) > 2 7 < 12 lsb av ss = 0v, av dd = 3.3v offset error (shared core) > -2 3 < 8 lsb ad25a monotonicity guaranteed note 1: these parameters are not characterized or tested in manufacturing. 2: no missing codes, limits based on characterization results. 3: these parameters are characterized but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is ensured, but not characterized. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 344 ? 2013-2015 microchip technology inc. adc accuracy: single-ended input ad20b nr resolution 12 bits ad21b inl integral nonlinearity > -3 < 3 lsb av ss = 0v, av dd = 3.3v ad22b dnl differential nonlinearity > -1 < 1.5 lsb av ss = 0v, av dd = 3.3v ( note 2 ) ad23b g err gain error (dedicated core) > 5 13 < 20 lsb av ss = 0v, av dd = 3.3v gain error (shared core) > -1 5 < 10 lsb ad24b e off offset error (dedicated core) > 2 10 < 18 lsb av ss = 0v, av dd = 3.3v offset error (shared core) > 2 8 < 15 lsb ad25b monotonicity guaranteed dynamic performance ad31b sinad signal-to-noise and distortion 63 > 65 db ( notes 3 , 4 ) ad34b enob effective number of bits 10.3 bits ( notes 3 , 4 ) table 26-43: adc module spe cifications (continued) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) ( 5 ) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characterized or tested in manufacturing. 2: no missing codes, limits based on characterization results. 3: these parameters are characterized but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is ensured, but not characterized. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 345 dspic33epxxgs50x family table 26-44: analog-to-digital co nversion timing requirements ac characteristics ( 2 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) ( 2 ) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min. typ. ( 1 ) max. units conditions clock parameters ad50 t ad adc clock period 14.28 n s throughput rate ad51 f tp sh0-sh3 3.25 msps 70 mhz adc clock, 12 bits, no pending conversion at time of trigger sh4 3.25 msps note 1: these parameters are characterized but not tested in manufacturing. 2: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is ensured, but not characterized. table 26-45: high-speed analog co mparator module specifications ac/dc characteristics ( 2 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units comments cm10 v ioff input offset voltage 5 mv cm11 v icm input common-mode voltage range ( 1 ) 0a v dd v cm13 cmrr common-mode rejection ratio 60 db cm14 t resp large signal response 15 ns v+ input step of 100 mv while v- input is held at av dd /2. delay measured from analog input pin to pwmx output pin. cm15 v hyst input hysteresis 5 10 20 mv depends on hyssel<1:0> cm16 t on comparator enabled to valid output 1 s note 1: these parameters are for design guidance only and are not tested in manufacturing. 2: the comparator module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 346 ? 2013-2015 microchip technology inc. table 26-46: dacx module specifications ac/dc characteristics ( 2 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units comments da01 extref external voltage reference ( 1 ) 0a v dd v da02 cv res resolution 12 bits da03 inl integral nonlinearity error -16 -12 0 lsb da04 dnl differential nonlinearity error -1.8 1 1.8 lsb da05 eoff offset error -8 3 15 lsb da06 eg gain error -1.2 -0.5 0 % da07 t set settling time ( 1 ) 700 ns output with 2% of desired output voltage with a 10-90% or 90-10% step note 1: parameters are for design guidance only and are not tested in manufacturing. 2: the dacx module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. table 26-47: dacx output (dacoutx pin) specifications dc characteristics ( 1 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units comments da11 r load resistive output load impedance 10k ohm da11a c load output load capacitance 35 pf including output pin capacitance da12 i out output current drive strength 300 a sink and source da13 v range output drive voltage range at current drive of 300 a av ss + 250 mv av dd C 900 mv v da14 v lrange output drive voltage range at reduced current drive of 50 a av ss + 50 mv av dd C 500 mv v da15 i dd current consumed when module is enabled 1.3 x i out a module will always consume this current, even if no load is connected to the output da30 v offset input offset voltage ? 5m v note 1: the dacx module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 347 dspic33epxxgs50x family table 26-48: pgax mo dule specifications ac/dc characteristics ( 1 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units comments pa01 v in input voltage range av ss C 0.3 av dd + 0.3 v pa02 v cm common-mode input voltage range av ss a v dd C 1.6 v pa03 v os input offset voltage -10 10 mv pa04 v os input offset voltage drift with temperature ? 15 v/ ? c pa05 r in + input impedance of positive input >1m || 7 pf ? || pf pa06 r in - input impedance of negative input 10k || 7 pf ? || pf pa07 g err gain error -2 2 % gain = 4x, 8x -3 3 % gain = 16x -4 4 % gain = 32x, 64x pa08 l err gain nonlinearity error 0.5 % % of full scale, gain = 16x pa09 i dd current consumption 2.0 ma module is enabled with a 2-volt p-p output voltage swing pa10a bw small signal bandwidth (-3 db) g = 4x 10 mhz pa10b g = 8x 5 mhz pa10c g = 16x 2.5 mhz pa10d g = 32x 1.25 mhz pa10e g = 64x 0.625 mhz pa11 ost output settling time to 1% of final value 0.4 s gain = 16x, 100 mv input step change pa12 sr output slew rate 40 v/s gain = 16x pa13 t gsel gain selection time 1 s pa14 t on module turn on/setting time 10 s note 1: the pgax module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. table 26-49: constant-curre nt source specifications dc characteristics ( 1 ) standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions cc01 i dd current consumption 30 a cc02 i reg regulation of current with voltage on 3% cc03 i out current output at terminal 10 a note 1: the constant-current source module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 348 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 349 dspic33epxxgs50x family 27.0 dc and ac device characteristics graphs figure 27-1: v oh C 4x driver pins figure 27-2: v oh C 8x driver pins figure 27-3: v ol C 4x driver pins figure 27-4: v ol C 8x driver pins note: the graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs, the data presented ma y be out side the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 ioh(a) voh (v) -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) 3v 3.3v 3.6v absolute maximum -0.080 -0.070 -0.060 -0.050 -0.040 0 030 ioh(a) voh (v) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) 3v 3.3v 3.6v absolute maximum 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 ioh(a) vol (v) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol (v) 3v 3.3v 3.6v absolute maximum iol(a) 0020 0.030 0.040 0.050 0.060 0.070 0.080 ioh(a) vol (v) 8x 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol (v) 8x 3v 3.3v 3.6v absolute maximum iol(a) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 350 ? 2013-2015 microchip technology inc. figure 27-5: typical i pd current @ v dd = 3.3v figure 27-6: typical i dd current @ v dd = 3.3v, +25c figure 27-7: typical i doze current @ v dd = 3.3v, +25c figure 27-8: typical i idle current @ v dd = 3.3v, +25c 0 50 100 150 200 250 300 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) i pd (a) 5 10 15 20 25 30 10 20 30 40 50 60 70 mips i dd (ma) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 doze ratio i doze (ma) 1:1 1:2 1:64 1:128 0.0 2.0 4.0 6.0 8.0 10.0 12.0 10 20 30 40 50 60 70 mips i idle (ma) downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 351 dspic33epxxgs50x family figure 27-9: typical frc frequency @ v dd = 3.3v figure 27-10: typical lprc frequency @ v dd = 3.3v 7150 7200 7250 7300 7350 7400 - 4 0- 2 00 2 04 06 08 01 0 01 2 0 temperature (c) frequency (khz) 33 33.2 33.4 33.6 33.8 34 34.2 34.4 -40 -20 0 20 40 60 80 100 120 temperature (c) frequency (khz) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 352 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 353 dspic33epxxgs50x family 28.0 packaging information 28.1 package marking information 28-lead soic (.300) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic33ep64gs502 1510017 28-lead uqfn (6x6x0.55 mm) xxxxxxxx 28-lead qfn-s (6x6x0.9 mm) xxxxxxxx yywwnnn 33ep64gs example 502 1510017 xxxxxxxx xxxxxxxx yywwnnn 33ep64gs 502 1510017 example legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 354 ? 2013-2015 microchip technology inc. 28.1 package marking information (continued) 44-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33ep 64gs504 1510017 xxxxxxxxxxx 44-lead qfn (8x8 mm) xxxxxxxxxxx xxxxxxxxxxx yywwnnn dspic33ep example 64gs504 1510017 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33ep 64gs506 1510017 48-lead tqfp (7x7x1.0 mm) example 1 xxxxxxx xxxyyww nnn 1 33ep64gs 5051510 017 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 355 dspic33epxxgs50x family 28.2 package details note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 356 ? 2013-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 357 dspic33epxxgs50x family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 358 ? 2013-2015 microchip technology inc. b a 0.10 c 0.10 c 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 1 2 n 2x top view side view bottom view note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c microchip technology drawing c04-385a sheet 1 of 2 2x 28x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 28-lead ultra thin plastic quad flat, no lead package (2n) - 6x6x0.55 mm body [uqfn] d e e2 d2 2x p 28x b e 28x l a (a3) a1 28x k with 4.65x4.65 mm exposed pad downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 359 dspic33epxxgs50x family microchip technology drawing c04-385a sheet 2 of 2 number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 a3 e l e n 0.65 bsc 0.127 ref 4.554.55 0.30 0.25 0.45 0.00 0.30 6.00 bsc 0.40 4.65 4.65 0.500.02 6.00 bsc millimeters min nom 28 4.754.75 0.50 0.35 0.550.05 max k- 0.20 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1.2. 3. noes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: exposed pad corner chamfer p - 0.35 - 28-lead ultra thin plastic quad flat, no lead package (2n) - 6x6x0.55 mm body [uqfn] with 4.65x4.65 mm exposed pad downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 360 ? 2013-2015 microchip technology inc. recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 4.75 4.75 millimeters 0.65 bsc min e max 6.00 contact pad length (x28) contact pad width (x28) y1 x1 0.80 0.35 microchip technology drawing c04-2385a nom silk screen c1 contact pad spacing 6.00 contact pad to pad (x28) g1 0.20 thermal via diameter v thermal via pitch ev 0.331.20 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1.2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: c2 c1 ev ev e y2 y2 y1 g2 g1 ?v x1 contact pad to center pad (x28) g2 0.20 28-lead ultra thin plastic quad flat, no lead package (2n) - 6x6x0.55 mm body [uqfn] with 4.65x4.65 mm exposed pad 12 28 note: corner anchor pads are not connected internally and are designed as mechanical features when the package is soldered to the pcb. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 361 dspic33epxxgs50x family downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 362 ? 2013-2015 microchip technology inc. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 363 dspic33epxxgs50x family

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dspic33epxxgs50x family ds70005127c-page 364 ? 2013-2015 microchip technology inc. b a 0.20 h a b 0.20 h a b 44 x b 0.20 c a b (datum b) (datum a) c seating plane 2x top view side view bottom view microchip technology drawing c04-076c sheet 1 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: e note 1 12 n d d1 e e1 2x a2 a1 a 0.10 c 3 n aa 0.20 c a b 4x 11 tips 123 44-lead plastic thin quad flatpack (pt) - 10x10x1.0 mm body [tqfp] note 1 note 2 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 365 dspic33epxxgs50x family microchip technology drawing c04-076c sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: l (l1) c section a-a h number of leads overall height lead width overall width overall length lead length molded package width molded package length molded package thickness lead pitch standoff units dimension limits a1 a b d e1 d1 a2 e l e n 0.80 bsc 0.45 0.30 - 0.05 0.37 12.00 bsc 0.60 10.00 bsc 10.00 bsc -- 12.00 bsc millimeters min nom 44 0.75 0.45 1.200.15 max 0.95 1.00 1.05 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2.3. noes: pin 1 visual index feature may vary, but must be located within the hatched area. exact shape of each corner is optional. dimensioning and tolerancing per asme y14.5m footprint l1 1.00 ref 3.5 0 7 foot angle lead thickness c 0.09 - 0.20 44-lead plastic thin quad flatpack (pt) - 10x10x1.0 mm body [tqfp] downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 366 ? 2013-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 367 dspic33epxxgs50x family downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 368 ? 2013-2015 microchip technology inc. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 369 dspic33epxxgs50x family downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 370 ? 2013-2015 microchip technology inc. c seating plane for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 microchip technology drawing c04-183a sheet 1 of 2 48-lead thin quad flatpack (pt) - 7x7x1.0 mm body [tqfp] with exposed pad top view e e1 d 0.20 h a-b d 4x d1/2 12 a b a a d d1 a1 a h 0.10 c 0.08 c side view d2 e2 n 12 n 0.20 c a-b d 48x tips 0.20 h a-b d 4x 0.20 4x e1/4 d1/4 a2 top view e1/2 e 48x b 0.08 c a-b d e/2 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 371 dspic33epxxgs50x family microchip technology drawing c04-183a sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 48-lead thin quad flatpack (pt) - 7x7x1.0 mm body [tqfp] with exposed pad h l (l1) t c d e section a-a 2. 1.4. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. 3. protrusions shall not exceed 0.25mm per side. mold draft angle bottom molded package thickness dimension limits mold draft angle top noes: foot length lead width lead thickness molded package length molded package width overall length overall width foot angle footprint standoff overall height lead pitch number of leads 12 e 11 13 0.75 0.60 0.45 l 12 0.22 7.00 bsc 7.00 bsc 9.00 bsc 9.00 bsc 3.5 1.00 ref c d b d1 e1 0.090.17 11 d e i l1 0 13 0.27 0.16 - 7 1.00 0.50 bsc 48 nom millimeters a1a2 a e 0.050.95 - units n min 1.05 0.15 1.20 - - max chamfers at corners are optional; size may vary. pin 1 visual index feature may vary, but must be located within the hatched area. dimensioning and tolerancing per asme y14.5m dimensions d1 and e1 do not include mold flash or protrusions. mold flash or exposed pad length exposed pad width d2 e2 3.50 bsc 3.50 bsc downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 372 ? 2013-2015 microchip technology inc. recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: c2 y2 x1 c1 x2 e y1 dimension limits units c1 optional center tab width contact pad spacing contact pad spacing optional center tab length contact pitch c2 y2 x2 3.50 3.50 millimeters 0.50 bsc min e max 8.408.40 contact pad length (x48) contact pad width (x48) y1 x1 1.50 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing no. c04-2183a nom 48-lead thin quad flatpack (pt) - 7x7x1.0 mm body [tqfp] with thermal tab downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 373 dspic33epxxgs50x family 0.20 c a-b d 64 x b 0.08 c a-b d c seating plane 4x n/4 tips top view side view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-085c sheet 1 of 2 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] d e e1 d1 d a b 0.20 h a-b d 4x d1/2 e a 0.08 c a1 a2 see detail 1 a a e1/2 note 1 note 2 1 2 3 n 0.05 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 374 ? 2013-2015 microchip technology inc. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] 13 12 11 e mold draft angle bottom 13 12 11 d mold draft angle top 0.27 0.22 0.17 b lead width 0.20 - 0.09 c lead thickness 10.00 bsc d1 molded package length 10.00 bsc e1 molded package width 12.00 bsc d overall length 12.00 bsc e overall width 7 3.5 0 i foot angle 0.75 0.60 0.45 l foot length 0.15 - 0.05 a1 standoff 1.05 1.00 0.95 a2 molded package thickness 1.20 - - a overall height 0.50 bsc e lead pitch 64 n number of leads max nom min dimension limits millimeters units footprint l1 1.00 ref 2. chamfers at corners are optional; size may vary. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 4. dimensioning and tolerancing per asme y14.5m bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25mm per side. noes: microchip technology drawing c04-085c sheet 2 of 2 l (l1) e c h x x=a?b or d e/2 detail 1 section a-a t downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 375 dspic33epxxgs50x family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 376 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 377 dspic33epxxgs50x family appendix a: revision history revision a (june 2013) this is the initial released version of the document. revision b (may 2015) adds dspic33epxxgs505 (48-pin) devices to the document: amends the table on page 2 to add the three new devices of this group adds the 48-pin tqfp pin diagram on page 7 amends tab l e 2 6- 3 to include thermal packaging characteristics for 48-pin packages updates section 28.1 package marking infor- mation to include package marking details for 48-pin tqfp devices updates section 28.2 package details to include microchip drawings c04-183a and c04-2183a (7x7x1.0 mm 48-lead tqfp) changes all references to dual boot flash program memory throughout the text to dual partition flash program memory. in addition, all accompanying refer- ences to panels and boot modes are changed to partitions and partition modes. this includes, but is not limited, to: section 4.1 program address space section 5.4 dual partition flash configuration , and register 5-1 section 23.10 code protection and codeguard? security , and ta b l e 2 3 - 2 replaces the high-speed pipeline a/d converter present in pre-production samples with a high-speed, multiple sar a/d converter in production devices: replaces section 19.0 high-speed, 12-bit analog-to-digital converter (adc) with an entirely new section of the same title, replacing all previous figures and registers updates the summary bullet points under high-speed adc module on page 1 to reflect the feature set of the new module updates ta b l e 4 - 3 and tab l e 7 - 1 to reflect the new modules interrupt structure replaces table 4-16 with a new register map removes table 4-16 (adc calibration register map); subsequent tables are renumbered accordingly updates section 23.2 device calibration and identification and table 23-3 to remove the adcal registers from the calibration register table removes all references to the internal tempera- ture sensor, including table 26-44 (temperature sensor specifications) and figure 27-11 (typical temperature sensor voltage vs. current) changes the esr specification of the v cap filter capacitor from < 4 ? to < 0.5 ? . removes the internal voltage reference in all occur- rences. for analog modules, the internal band gap reference is substituted as a replacement source. changes the following register names in all occurrences throughout the text: cmpconx to cmpxcon cmpdacx to cmpxdac i2cxcon1 to i2cxconl i2cxcon2 to i2cxconh updates the text of section 5.4.2 dual partition modes to change untrusted dual panel mode to privileged dual partition mode and clarifies the modes code security features. changes the bss2 configuration bit to bsen throughout the text. replaces section 23.3 user otp memory with new text to describe the 64-word user otp memory space; also removes table 23-4. amends ta b l e 2 4 - 2 with a footnote indicating an increase of instruction execution cycles for most instructions under certain conditions. updates the following tables in section 26.0 electrical characteristics (in addition to changes previously noted): table 26-4 , with new specification dc12 (and accompanying footnote) table 26-6 , with updated typical and new maxi- mum data throughout, and the addition of parameter dc27 (with accompanying footnote) table 26-7 , tab l e 2 6- 8 and table 26-10 with updated typical and maximum data throughout table 26-9 with updated typical and maximum data for parameters dc61a and dc61b footnotes 6 and 7 of ta b l e 2 6 - 11 to clarify the behavior of 5v tolerant pins the adc accuracy specifications of table 26-43 table 26-45 (table 26-45 in revision a) with updated specifications for parameter cm15 table 26-46 (table 26-46 in revision a) with updated specifications for parameters da03 through da06 clarifies the text of footnotes 6 and 7 in tab le 2 6- 11 (i/o pin input specifications). removes the reference inputs specifications from table 26-43 in their entirety. replaces figure 27-5 through figure 27-10 with new characterization graphs to reflect the most current data and removes tbd watermarks. updates section 28.1 package marking informa- tion to reflect the removal of redundant temperature and package code information from all package markings; this is in addition to the new 48-pin package markings previously described. other minor typographic corrections throughout the document. downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 378 ? 2013-2015 microchip technology inc. revision c (october 2015) updates note 2 in tab le 1 -1 . updates figure 2-5 . inserts new section 4.2 unique device identifier (udid) and adds table 4-1 . subsequent tables were renumbered accordingly. updates ta b l e 4 - 3 (which was table 4-2), tab le 4 -5 (which was table 4-4), table 4-10 (which was table 4-9), ta b l e 4 - 11 (which was table 4-10), ta b l e 4 - 2 1 (which was table 4-20), table 4-32 (which was table 4-31), tab le 4 -3 6 (which was table 4-35) and table 4-37 (which was table 4-36). updates section 4.8.1 bit-reversed addressing implementation (which was section 4.7.1). updates register 9-1 . updates figure 12-2 and register 12-2 . updates register 13-1 . updates note 1 in section 14.0 output compare . updates register 15-1 , register 15-6 , register 15-20 and register 15-22 . updates figure 17-1 . updates register 18-2 . updates figure 19-2 and figure 19-3 . updates register 19-1 , register 19-2 , register 19-3 , register 19-4 , register 19-26 and register 19-33 . adds register 19-27 . updates figure 21-2 . updates section 23.6.2 sleep and idle modes . updates table 26-8 , table 26-11 , table 26-29 . adds new table 26-42 . subsequent tables were renumbered accordingly. updates table 26-43 (which was table 26-42), table 26-46 (which was table 26-45) and table 26-48 (which was table 26-47). updated diagrams in section 28.0 packaging information . updates the product identification system section. other minor typographic corrections throughout the document. downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 379 dspic33epxxgs50x family index a absolute maximum ratings .............................................. 303 ac characteristics ............................................................ 315 adc specifications ................................................... 343 analog current specifications................................... 342 analog-to-digital conversion requirements............. 345 auxiliary pll clock ................................................... 317 capacitive loading requirements on output pins ....................................................... 315 external clock requirements ................................... 316 high-speed pwmx requirements ............................ 325 i/o requirements............................................. ......... 319 i2cx bus data requirements (master mode) ........... 339 i2cx bus data requirements (slave mode) ............. 341 input capture x requirements .................................. 323 internal frc accuracy.............................................. 318 internal lprc accuracy............................................ 318 load conditions ............................................... ......... 315 ocx/pwmx module requirements ........................... 324 output compare x requirements ............................. 324 pll clock.................................................................. 317 reset, wdt, ost, pwrt requirements ................. 320 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) requirements .................... 329 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) requirements .................... 328 spix master mode (half-duplex, transmit only) requirements ........................... 327 spix maximum data/clock rate summary .............. 326 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) requirements .................... 337 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) requirements .................... 335 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) requirements .................... 331 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) requirements .................... 333 temperature and voltage specifications .................. 315 timer1 external clock requirements ....................... 321 timer2/timer4 external clock requirements ........... 322 timer3/timer5 external clock requirements ........... 322 uartx i/o requirements ........................................ . 342 ac/dc characteristics dacx specifications ................................................. 346 high-speed analog comparator specifications........ 345 pgax specifications ................................................. 347 analog-to-digital converter. see adc. arithmetic logic unit (alu)................................................. 30 assembler mpasm assembler................................................... 300 mplab assembler, linker, librarian ........................ 300 b bit-reversed addressing .................................................... 73 example ...................................................................... 74 implementation ........................................................... 73 sequence table (16-entry)......................................... 74 block diagrams 16-bit timer1 module.......................................... ...... 163 adc module.............................................................. 230 adc shared core ..................................................... 231 addressing for table registers .................................. 77 call stack frame ..................................................... 69 connections for on-chip voltage regulator ............ 285 constant-current source.......................................... 275 cpu core ................................................................... 22 data access from program space address generation............................................ 75 dedicated adc cores 0-3 ........................................ 231 dspic33epxxgs50x family ..................................... 11 high-speed analog comparator x............................ 264 high-speed pwm architecture................................. 183 hysteresis control .................................................... 266 i2cx module ............................................. ................ 216 input capture x ......................................................... 171 interleaved pfc.......................................................... 18 mclr pin connections ............................................ .. 16 multiplexing remappable outputs for rpn .............. 130 off-line ups .............................................................. 20 oscillator system...................................................... 104 output compare x module ....................................... 175 pgax functions........................................................ 272 pgax module .............................................. ............. 271 phase-shifted full-bridge converter.......................... 19 pll module .............................................................. 105 programmers model ............................................... ... 24 psv read address generation.................................. 66 recommended minimum connection ........................ 16 remappable input for u1rx .................................... 128 reset system ............................................................. 85 security segments for dspic33ep64gs50x ........... 288 security segments for dspic33ep64gs50x (dual partition mode)........................................ 288 shared port structure............................................... 125 simplified conceptual of high-speed pwm ............. 184 spix module .............................................. ............... 207 suggested oscillator circuit placement ..................... 17 timerx (x = 2 through 5) ......................................... .. 168 type b/type c timer pair (32-bit timer) ................. 168 uartx module .............................................. ........... 223 watchdog timer (wdt)......................................... ... 286 brown-out reset (bor)......................................... ... 277, 285 c c compilers mplab xc ............................................................... 300 code examples port write/read ........................................................ 126 pwm write-protected register unlock sequence ............................................. 182 pwrsav instruction syntax .................................... 115 code protection ............................................... ......... 277, 287 codeguard security .............................................. ... 277, 287 configuration bits ..................................................... ........ 277 description................................................................ 280 configuration register map .............................................. 278 constant-current source.................................................. 275 control register........................................................ 276 description................................................................ 275 features overview ................................................... 275 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 380 ? 2013-2015 microchip technology inc. cpu addressing modes ................................................. ..... 21 clocking system options.......................................... 105 fast rc (frc) oscillator .................................. 105 frc oscillator with pll (frcpll)................... 105 frc oscillator with postscaler ......................... 105 low-power rc (lprc) oscillator..................... 105 primary (xt, hs, ec) oscillator........................ 105 primary oscillator with pll............................... 105 control registers ........................................................ 26 data space addressing .............................................. 21 instruction set ............................................................. 21 registers..................................................................... 21 resources................................................................... 25 customer change notification service ............................. 384 customer notification service........................................... 384 customer support ............................................... .............. 384 d data address space ........................................................... 37 memory map for dspic33ep16gs50x devices ......... 38 memory map for dspic33ep32gs50x devices ......... 39 memory map for dspic33ep64gs50x devices ......... 40 near data space ........................................................ 37 organization, alignment............................................ .. 37 sfr space.................................................................. 37 width........................................................................... 37 data space extended x ................................................ ................. 69 paged data memory space (figure) ........................... 67 paged memory scheme ............................................ . 66 dc characteristics brown-out reset (bor) ............................................ 313 constant-current source specifications ................... 347 dacx output (dacoutx pin) specifications ........... 346 doze current (i doze ) ................................................ 309 i/o pin input specifications ..................................... .. 310 i/o pin output specifications .................................... 313 idle current (i idle ) .................................................... 307 operating current (i dd )............................................. 306 operating mips vs. voltage...................................... 304 power-down current (i pd ) ........................................ 308 program memory ...................................................... 314 temperature and voltage specifications .................. 305 watchdog timer delta current ( ? i wdt ) .................... 308 dc/ac characteristics graphs and tables .............................................. ..... 349 demo/development boards, evaluation and starter kits ................................................................ 302 development support ............................................... ........ 299 device calibration ............................................................. 283 addresses ................................................................. 283 and identification ........................................... ............ 283 device programmer mplab pm3 ............................................................. 301 doze mode........................................................................ 117 dsp engine......................................................................... 30 e electrical characteristics................................................... 303 ac ............................................................................. 315 equations device operating frequency .................................... 105 f pllo calculation...................................................... 105 f vco calculation....................................................... 105 errata .................................................................................. 10 f filter capacitor (c efc ) specifications .............................. 305 flash program memory ...................................................... 77 and table instructions ........................................... ..... 77 control registers ...................................................... .. 80 dual partition flash configuration .............................. 79 operations .................................................................. 78 resources .................................................................. 79 rtsp operation ......................................................... 78 flexible configuration ....................................................... 277 g getting started guidelines.................................................. 15 connection requirements .......................................... 15 cpu logic filter capacitor connection (v cap ) .......... 16 decoupling capacitors................................................ 15 external oscillator pins............................................... 17 icsp pins ................................................................... 17 master clear (mclr ) pin ........................................... 16 oscillator value conditions on start-up...................... 18 targeted applications ................................................. 18 unused i/os................................................................ 18 h high-speed analog comparator applications .............................................................. 265 description................................................................ 264 digital-to-analog comparator (dac) ........................ 265 features overview.................................................... 263 hysteresis................................................................. 266 pulse stretcher and digital logic.............................. 265 resources ................................................................ 266 high-speed pwm description................................................................ 181 features ................................................................... 181 resources ................................................................ 182 write-protected registers......................................... 182 high-speed, 12-bit analog-to-digital converter (adc) ....................................................... 229 control registers ...................................................... 232 features overview.................................................... 229 resources ................................................................ 232 i i/o ports............................................................................ 125 configuring analog/digital port pins......................... 126 helpful tips............................................................... 132 open-drain configuration......................................... 126 parallel i/o (pio) ...................................................... 125 resources ................................................................ 133 write/read timing .......................................... .......... 126 in-circuit debugger............................................. .............. 287 mplab icd 3 ........................................................... 301 pickit 3 programmer ................................................ 301 in-circuit emulation .......................................................... 277 in-circuit serial programming (icsp)....................... 277, 287 input capture .................................................................... 171 control registers ...................................................... 172 resources ................................................................ 171 input change notification (icn)................................... ..... 126 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 381 dspic33epxxgs50x family instruction addressing modes......................................... .... 70 file register instructions ............................................ 70 fundamental modes supported.................................. 70 mac instructions......................................................... 71 mcu instructions ........................................................ 70 move and accumulator instructions............................ 71 other instructions........................................................ 71 instruction set summary................................................... 289 overview ................................................................... 292 symbols used in opcode descriptions..................... 290 instruction-based power-saving modes ........................... 115 idle ............................................................................ 116 sleep......................................................................... 116 inter-integrated circuit (i 2 c).............................................. 215 control registers ...................................................... 217 resources................................................................. 215 inter-integrated circuit. see i 2 c. internet address................................................................ 384 interrupt controller alternate interrupt vector table (aivt) ...................... 89 control and status registers ...................................... 94 intcon1 ............................................................ 94 intcon2 ............................................................ 94 intcon3 ............................................................ 94 intcon4 ............................................................ 94 inttreg ............................................................ 94 interrupt vector details ............................................... 92 interrupt vector table (ivt) ........................................ 89 reset sequence ................................................ ......... 89 resources................................................................... 94 interrupts coincident with power save instructions.......... 116 j jtag boundary scan interface ....................................... . 277 jtag interface.................................................................. 287 l leading-edge blanking (leb)........................................... 181 lprc oscillator use with wdt ........................................................... 286 m memory organization............................................ .............. 31 resources................................................................... 41 microchip internet web site.............................................. 384 modulo addressing ................................................. ............ 72 applicability ................................................................. 73 operation example ..................................................... 72 start and end address............................................. ... 72 w address register selection .................................... 72 mplab real ice in-circuit emulator system................. 301 mplab x integrated development environment software............................................... 299 mplink object linker/mplib object librarian ................ 300 o oscillator control registers ...................................................... 107 resources................................................................. 106 output compare ............................................................... 175 control registers ...................................................... 176 resources................................................................. 175 p packaging......................................................................... 353 details....................................................................... 355 marking..................................................................... 353 peripheral module disable (pmd) .................................... 117 peripheral pin select (pps)........................................... ... 127 available peripherals.............................................. .. 127 available pins ........................................................... 12 7 control ...................................................................... 127 control registers...................................................... 134 input mapping............................................... ............ 128 output mapping ............................................. ........... 130 output selection for remappable pins .................... 131 selectable input sources.......................................... 129 pinout i/o descriptions (table)................................... ......... 12 power-saving features .................................................... 115 clock frequency and switching ............................... 115 resources ................................................................ 117 program address space..................................................... 31 construction ............................................................... 75 data access from program memory using table instructions ............................................... 76 memory map (dspic33ep16gs50x devices) ........... 32 memory map (dspic33ep32gs50x devices) ........... 33 memory map (dspic33ep64gs50x devices, dual partition)..................................................... 35 memory map (dspic33ep64gs50x devices) ........... 34 table read high instructions (tblrdh) ................... 76 table read low instructions (tblrdl) ..................... 76 program memory interfacing with data memory spaces........................ 75 organization .............................................. ................. 36 reset vector............................................................... 36 programmable gain amplifier (pga)................................ 271 description................................................................ 272 resources ................................................................ 273 programmable gain amplifier. see pga. programmers model ............................................... ........... 23 register descriptions ................................................. 23 r register maps adc ............................................................................ 54 analog comparator .................................................... 61 constant-current source............................................ 60 cpu core ................................................................... 42 i2c1 and i2c2 ........................................... ................. 52 input capture 1 through input capture 4.................... 47 interrupt controller...................................................... 44 jtag interface ........................................................... 61 nvm............................................................................ 59 output compare 1 through output compare 4 .......... 48 peripheral pin select input ......................................... 58 peripheral pin select output (dspic33epxxgs502 devices)......................... 56 peripheral pin select output (dspic33epxxgs504/505 devices).................. 56 peripheral pin select output (dspic33epxxgs506 devices)......................... 57 pmd............................................................................ 60 porta (dspic33epxxgs502 devices) ................... 62 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 382 ? 2013-2015 microchip technology inc. porta (dspic33epxxgs504/505 devices) ............. 63 porta (dspic33epxxgs506 devices) .................... 64 portb (dspic33epxxgs502 devices) .................... 62 portb (dspic33epxxgs504/505 devices) ............. 63 portb (dspic33epxxgs506 devices) .................... 64 portc (dspic33epxxgs504/505 devices)............. 63 portc (dspic33epxxgs506 devices).................... 64 portd (dspic33epxxgs506 devices).................... 65 programmable gain.................................................... 60 pwm ........................................................................... 49 pwm generator 1 ............................................. .......... 49 pwm generator 2 ............................................. .......... 50 pwm generator 3 ............................................. .......... 50 pwm generator 4 ............................................. .......... 51 pwm generator 5 ............................................. .......... 51 spi1 and spi2 ........................................... ................. 53 system control ........................................................... 59 timer1 through timer5 ........................................ ....... 46 uart1 and uart2 .............................................. ...... 52 registers aclkcon (auxiliary clock divisor control) ............. 112 adcal0l (adc calibration 0 high) ......................... 256 adcal0l (adc calibration 0 low) .......................... 255 adcal1h (adc calibration 1 high) ......................... 257 adcmpxcon (adc digital comparator x control) ............................................................. 258 adcmpxenh (adc digital comparator x channel enable high)....................................... 259 adcmpxenl (adc digital comparator x channel enable low)........................................ 259 adcon1h (adc control 1 high) ............................. 233 adcon1l (adc control 1 low) ............................... 232 adcon2h (adc control 2 high) ............................. 235 adcon2l (adc control 2 low) ............................... 234 adcon3h (adc control 3 high) ............................. 237 adcon3l (adc control 3 low) ............................... 236 adcon4h (adc control 4 high) ............................. 239 adcon4l (adc control 4 low) ............................... 238 adcon5h (adc control 5 high) ............................. 241 adcon5l (adc control 5 low) ............................... 240 adcorexh (dedicated adc core x control high)..................................................... 243 adcorexl (dedicated adc core x control low)...................................................... 242 adeieh (adc early interrupt enable high) ............. 245 adeiel (adc early interrupt enable low) ............... 245 adeistath (adc early interrupt status high)........ 246 adeistatl (adc early interrupt status low) ......... 246 adflxcon (adc digital filter x control)................. 260 adieh (adc interrupt enable high) ......................... 249 adiel (adc interrupt enable low) .......................... 249 adlvltrgh (adc level-sensitive trigger control high)..................................................... 244 adlvltrgl (adc level-sensitive trigger control low)...................................................... 244 admod0h (adc input mode control 0 high) .......... 247 admod0l (adc input mode control 0 low) ........... 247 admod1l (adc input mode control 1 low) ........... 248 adstath (adc data ready status high)............... 250 adstatl (adc data ready status low) ................ 250 adtrigxh (adc channel trigger x selection high).................................................. 253 adtrigxl (adc channel trigger x selection low) .................................................. 251 altdtrx (pwmx alternate dead-time) .................. 197 auxconx (pwmx auxiliary control) ....................... 205 chop (pwmx chop clock generator)..................... 190 clkdiv (clock divisor) ............................................ 109 cmpxcon (comparator x control) .......................... 267 cmpxdac (comparator x dac control) .................. 269 corcon (core control) ...................................... 28, 96 ctxtstat (cpu w register context status)........... 29 devid (device id).................................................... 284 devrev (device revision)...................................... 284 dtrx (pwmx dead-time)........................................ 197 fclconx (pwmx fault current-limit control)........ 201 i2cxconh (i2cx control high) ................................ 219 i2cxconl (i2cx control low) ................................. 217 i2cxmsk (i2cx slave mode address mask) ............ 222 i2cxstat (i2cx status) ........................................... 220 icxcon1 (input capture x control 1)....................... 172 icxcon2 (input capture x control 2)....................... 173 intcon1 (interrupt control 1).................................... 97 intcon2 (interrupt control 2).................................... 99 intcon3 (interrupt control 3).................................. 100 intcon4 (interrupt control 4).................................. 100 inttreg (interrupt control and status) .................. 101 ioconx (pwmx i/o control).................................... 199 isrccon (constant-current source control) ......... 276 lebconx (pwmx leading-edge blanking control) .............................................. 203 lebdlyx (pwmx leading-edge blanking delay) ................................................ 204 lfsr (linear feedback shift) .................................. 114 mdc (pwmx master duty cycle) ............................. 191 nvmadr (nonvolatile memory lower address) .................................................. 83 nvmadru (nonvolatile memory upper address) ................................................. . 83 nvmcon (nonvolatile memory (nvm) control)......... 81 nvmkey (nonvolatile memory key) .......................... 84 nvmsrcadr (nvm source data address) .............. 84 ocxcon1 (output compare x control 1) ................ 176 ocxcon2 (output compare x control 2) ................ 178 osccon (oscillator control) ................................... 107 osctun (frc oscillator tuning)............................ 111 pdcx (pwmx generator duty cycle)....................... 194 pgaxcal (pgax calibration) .................................. 274 pgaxcon (pgax control) ....................................... 273 phasex (pwmx primary phase-shift)..................... 195 pllfbd (pll feedback divisor).............................. 110 pmd1 (peripheral module disable control 1)........... 118 pmd2 (peripheral module disable control 2)........... 119 pmd3 (peripheral module disable control 3)........... 120 pmd4 (peripheral module disable control 4)........... 120 pmd6 (peripheral module disable control 6)........... 121 pmd7 (peripheral module disable control 7)........... 122 pmd8 (peripheral module disable control 8)........... 123 ptcon (pwmx time base control) ........................ 185 ptcon2 (pwmx clock divider select 2) ................. 186 ptper (pwmx primary master time base period)............................................ 187 pwmcapx (pwmx primary time base capture) ......................................... 206 pwmconx (pwmx control)..................................... 192 pwmkey (pwmx protection lock/unlock key)....... 191 rcon (reset control)................................................ 87 refocon (reference oscillator control) ............... 113 rpinr0 (peripheral pin select input 0).................... 134 rpinr1 (peripheral pin select input 1).................... 134 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 383 dspic33epxxgs50x family rpinr11 (peripheral pin select input 11)................ 139 rpinr12 (peripheral pin select input 12)................ 140 rpinr13 (peripheral pin select input 13)................ 141 rpinr18 (peripheral pin select input 18)................ 142 rpinr19 (peripheral pin select input 19)................ 143 rpinr2 (peripheral pin select input 2).................... 135 rpinr20 (peripheral pin select input 20)................ 144 rpinr21 (peripheral pin select input 21)................ 145 rpinr22 (peripheral pin select input 22)................ 146 rpinr23 (peripheral pin select input 23)................ 147 rpinr3 (peripheral pin select input 3).................... 136 rpinr37 (peripheral pin select input 37)................ 148 rpinr38 (peripheral pin select input 38)................ 149 rpinr42 (peripheral pin select input 42)................ 150 rpinr43 (peripheral pin select input 43)................ 151 rpinr7 (peripheral pin select input 7).................... 137 rpinr8 (peripheral pin select input 8).................... 138 rpor0 (peripheral pin select output 0).................. 152 rpor1 (peripheral pin select output 1).................. 152 rpor10 (peripheral pin select output 10).............. 157 rpor11 (peripheral pin select output 11).............. 157 rpor12 (peripheral pin select output 12).............. 158 rpor13 (peripheral pin select output 13).............. 158 rpor14 (peripheral pin select output 14).............. 159 rpor15 (peripheral pin select output 15).............. 159 rpor16 (peripheral pin select output 16).............. 160 rpor17 (peripheral pin select output 17).............. 160 rpor18 (peripheral pin select output 18).............. 161 rpor2 (peripheral pin select output 2).................. 153 rpor3 (peripheral pin select output 3).................. 153 rpor4 (peripheral pin select output 4).................. 154 rpor5 (peripheral pin select output 5).................. 154 rpor6 (peripheral pin select output 6).................. 155 rpor7 (peripheral pin select output 7).................. 155 rpor8 (peripheral pin select output 8).................. 156 rpor9 (peripheral pin select output 9).................. 156 sdcx (pwmx secondary duty cycle) ...................... 194 sevtcmp (pwmx special event compare)............ 187 sphasex (pwmx secondary phase-shift).............. 196 spixcon1 (spix control 1)...................................... 211 spixcon2 (spix control 2)...................................... 213 spixstat (spix status and control) ....................... 209 sr (cpu status)............................................... 26, 95 ssevtcmp (pwmx secondary special event compare)................................................ 190 stcon (pwmx secondary master time base control)........................................... 188 stcon2 (pwmx secondary clock divider select 2)............................................................ 189 stper (pwmx secondary master time base period) ............................................ 189 strigx (pwmx secondary trigger compare value)................................................ 202 t1con (timer1 control)........................................... 165 trgconx (pwmx trigger control).......................... 198 trigx (pwmx primary trigger compare value)................................................ 200 txcon (timer2/4 control)........................................ 169 tycon (timer3/5 control)........................................ 170 uxmode (uartx mode).......................................... 225 uxsta (uartx status and control)......................... 227 resets ................................................................................ 85 brown-out reset (bor).............................................. 85 configuration mismatch reset (cm) .......................... 85 illegal condition reset (iopuwr) ............................. 85 illegal opcode .............................................. ...... 85 security .............................................................. 85 uninitialized w register ..................................... 85 master clear (mclr ) pin reset................................. 85 power-on reset (por)............................................... 85 reset instruction (swr) .......................................... 85 resources .................................................................. 86 trap conflict reset (trapr) ..................................... 85 watchdog timer time-out reset (wdto) ................. 85 revision history................................................................ 377 s serial peripheral interface (spi) ....................................... 207 serial peripheral interface. see spi. software simulator mplab x sim........................................................... 301 special features of the cpu ............................................ 277 spi control registers...................................................... 209 helpful tips............................................................... 208 resources ................................................................ 208 t thermal operating conditions.......................................... 304 thermal packaging characteristics .................................. 304 third-party development tools ........................................ 302 timer1 .............................................................................. 16 3 control register........................................................ 165 mode settings........................................................... 163 resources ................................................................ 164 timer2/3 and timer4/5 ...................................... ............... 167 control registers...................................................... 169 resources ................................................................ 167 timing diagrams bor and master clear reset characteristics .......... 319 external clock .......................................................... 316 high-speed pwmx fault characteristics ................. 325 high-speed pwmx module characteristics ............. 325 i/o characteristics .................................................... 319 i2cx bus data (master mode) .................................. 338 i2cx bus data (slave mode) .................................. .. 340 i2cx bus start/stop bits (master mode)................... 338 i2cx bus start/stop bits (slave mode)..................... 340 input capture x (icx) characteristics ....................... 323 ocx/pwmx characteristics ...................................... 324 output compare x (ocx) characteristics................. 324 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) ........................................... 329 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) ........................................... 328 spix master mode (half-duplex, transmit only, cke = 0) .................................. 326 spix master mode (half-duplex, transmit only, cke = 1) .................................. 327 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) ........................................... 336 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) ........................................... 334 downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 384 ? 2013-2015 microchip technology inc. spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) ........................................... 330 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) ........................................... 332 timer1-timer5 external clock characteristics.......... 321 uartx i/o characteristics........................................ 342 u unique device identifier (udid).......................................... 31 universal asynchronous receiver transmitter (uart)................................................... 223 control registers ...................................................... 225 helpful tips ............................................................... 224 resources................................................................. 224 universal asynchronous receiver transmitter. see uart. user otp memory ............................................................ 285 v voltage regulator (on-chip) ......................................... ... 285 w watchdog timer (wdt)......................................... ... 277, 286 programming considerations ........................... 286, 287 www address ................................................................. 384 www, on-line support ....... .............................................. 10 downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 385 dspic33epxxgs50x family the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 386 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 387 dspic33epxxgs50x family product identification system to order or obtain information, e.g., on pricing or del ivery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller flash memory family: ep = enhanced performance product group: gs = smps family pin count: 02 = 28-pin 04 = 44-pin 05 = 48-pin 06 = 64-pin temperature range: i=-40 ? c to +85 ? c (industrial) e=-40 ? c to +125 ? c (extended) package: ml = plastic quad, no lead package C (44-pin) 8x8 mm body (qfn) mm = plastic quad, no lead package C (28-pin) 6x6 mm body (qfn-s) mx = plastic quad flat, no lead package C (28-pin) 6x6 mm body (uqfn) pt = plastic thin quad flatpack C (44-pin) 10x10 mm body (tqfp) pt = plastic thin quad flatpack C (48-pin) 7x7 mm body (tqfp) pt = plastic thin quad flatpack C (64-pin) 10x10 mm body (tqfp) so = plastic small outline, wide C (28-pin) 7.50 mm body (soic) examples: dspic33ep64gs504-i/pt: dspic33, enhanced performance, 64-kbyte program memory, smps, 44-pin, industrial temperature, tqfp package. microchip trademark architecture flash memory family program memory size (kbyte) product group pin count temperature range package pattern dspic 33 ep 64 gs5 04 t - i / pt x xx tape and reel flag (if applicable) downloaded from: http:///
dspic33epxxgs50x family ds70005127c-page 388 ? 2013-2015 microchip technology inc. notes: downloaded from: http:///
? 2013-2015 microchip technology inc. ds70005127c-page 389 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-891-8 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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